r600/sfn: lower CLIPVERTEX to clip planes
With that most piglits for compatibility contexts are passing, so enable higher compatibility profile support. v2: fix formatting ahd fallthrough tag (Filip) Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Filip Gawin <filip@gawin.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17484>
This commit is contained in:
Gert Wollny
parent
19ba29d996
commit
3340c7ce35
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@ -358,7 +358,10 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
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return 4;
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case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
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if (!is_nir_enabled(&rscreen->b))
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return 140;
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FALLTHROUGH;
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case PIPE_CAP_GLSL_FEATURE_LEVEL:
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if (family >= CHIP_CEDAR)
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return is_nir_enabled(&rscreen->b) ? 450 : 430;
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@ -367,9 +370,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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return 330;
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return 140;
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case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
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return 140;
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/* Supported except the original R600. */
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case PIPE_CAP_INDEP_BLEND_ENABLE:
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case PIPE_CAP_INDEP_BLEND_FUNC:
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@ -284,6 +284,8 @@ static void r600_set_clip_state(struct pipe_context *ctx,
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rctx->clip_state.state = *state;
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r600_mark_atom_dirty(rctx, &rctx->clip_state.atom);
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rctx->driver_consts[PIPE_SHADER_VERTEX].vs_ucp_dirty = true;
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rctx->driver_consts[PIPE_SHADER_TESS_EVAL].vs_ucp_dirty = true;
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rctx->driver_consts[PIPE_SHADER_GEOMETRY].vs_ucp_dirty = true;
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}
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static void r600_set_stencil_ref(struct pipe_context *ctx,
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@ -1350,6 +1352,12 @@ void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_on
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start = compute_only ? PIPE_SHADER_COMPUTE : 0;
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end = compute_only ? PIPE_SHADER_TYPES : PIPE_SHADER_COMPUTE;
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int last_vertex_stage = PIPE_SHADER_VERTEX;
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if (rctx->tes_shader)
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last_vertex_stage = PIPE_SHADER_TESS_EVAL;
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if (rctx->gs_shader)
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last_vertex_stage = PIPE_SHADER_GEOMETRY;
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for (sh = start; sh < end; sh++) {
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struct r600_shader_driver_constants_info *info = &rctx->driver_consts[sh];
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if (!info->vs_ucp_dirty &&
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@ -1362,7 +1370,9 @@ void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_on
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ptr = info->constants;
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size = info->alloc_size;
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if (info->vs_ucp_dirty) {
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assert(sh == PIPE_SHADER_VERTEX);
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assert(sh == PIPE_SHADER_VERTEX ||
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sh == PIPE_SHADER_GEOMETRY ||
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sh == PIPE_SHADER_TESS_EVAL);
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if (!size) {
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ptr = rctx->clip_state.state.ucp;
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size = R600_UCP_SIZE;
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@ -1411,7 +1421,7 @@ void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_on
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if (info->texture_const_dirty) {
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assert (ptr);
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assert (size);
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if (sh == PIPE_SHADER_VERTEX)
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if (sh == last_vertex_stage)
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memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
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if (sh == PIPE_SHADER_FRAGMENT)
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memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
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@ -54,7 +54,6 @@ using std::vector;
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NirLowerInstruction::NirLowerInstruction():
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b(nullptr)
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{
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}
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bool NirLowerInstruction::filter_instr(const nir_instr *instr, const void *data)
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@ -191,6 +190,75 @@ void sort_fsoutput(nir_shader *shader)
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exec_list_append(&shader->variables, &new_list);
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}
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class LowerClipvertexWrite : public NirLowerInstruction {
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public:
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LowerClipvertexWrite(int noutputs, pipe_stream_output_info& so_info) :
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m_clipplane1(noutputs),
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m_clipvtx(noutputs + 1),
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m_so_info(so_info){}
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private:
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bool filter(const nir_instr *instr) const override {
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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auto intr = nir_instr_as_intrinsic(instr);
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if (intr->intrinsic != nir_intrinsic_store_output)
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return false;
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return nir_intrinsic_io_semantics(intr).location == VARYING_SLOT_CLIP_VERTEX;
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}
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nir_ssa_def *lower(nir_instr *instr) override {
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auto intr = nir_instr_as_intrinsic(instr);
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nir_ssa_def *output[8] = {nullptr};
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// for UBO loads we correct the buffer ID by adding 1
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auto buf_id = nir_imm_int(b, R600_BUFFER_INFO_CONST_BUFFER - 1);
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assert(intr->src[0].is_ssa);
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auto clip_vtx = intr->src[0].ssa;
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for (int i = 0; i < 8; ++i) {
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auto sel = nir_imm_int(b, i);
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auto mrow = nir_load_ubo_vec4(b, 4, 32, buf_id, sel);
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output[i] = nir_fdot4(b, clip_vtx, mrow);
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}
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unsigned clip_vertex_index = nir_intrinsic_base(intr);
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for (int i = 0; i < 2; ++i) {
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auto clip_i = nir_vec(b, &output[4 * i], 4);
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auto store = nir_store_output(b, clip_i, intr->src[1].ssa);
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nir_intrinsic_set_write_mask(store, 0xf);
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nir_intrinsic_set_base(store, clip_vertex_index);
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nir_io_semantics semantic = nir_intrinsic_io_semantics(intr);
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semantic.location = VARYING_SLOT_CLIP_DIST0 + i;
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semantic.no_varying = 1;
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if (i > 0)
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nir_intrinsic_set_base(store, m_clipplane1);
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nir_intrinsic_set_write_mask(store, 0xf);
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nir_intrinsic_set_io_semantics(store, semantic);
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}
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nir_intrinsic_set_base(intr, m_clipvtx);
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nir_ssa_def *result = NIR_LOWER_INSTR_PROGRESS_REPLACE;
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for (unsigned i = 0; i < m_so_info.num_outputs; ++i) {
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if (m_so_info.output[i].register_index == clip_vertex_index) {
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m_so_info.output[i].register_index = m_clipvtx;
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result = NIR_LOWER_INSTR_PROGRESS;
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}
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}
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return result;
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}
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int m_clipplane1;
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int m_clipvtx;
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pipe_stream_output_info& m_so_info;
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};
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}
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static nir_intrinsic_op
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@ -278,6 +346,19 @@ r600_lower_deref_instr(nir_builder *b, nir_instr *instr_, UNUSED void *cb_data)
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return true;
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}
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static bool
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r600_lower_clipvertex_to_clipdist(nir_shader *sh,
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pipe_stream_output_info& so_info)
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{
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if (!(sh->info.outputs_written & VARYING_BIT_CLIP_VERTEX))
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return false;
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int noutputs = util_bitcount64(sh->info.outputs_written);
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bool result = r600::LowerClipvertexWrite(noutputs, so_info).run(sh);
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return result;
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}
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static bool
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r600_nir_lower_atomics(nir_shader *shader)
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{
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@ -504,6 +585,22 @@ bool has_saturate(const nir_function *func)
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return false;
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}
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static bool r600_is_last_vertex_stage(nir_shader *nir, const r600_shader_key& key)
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{
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if (nir->info.stage == MESA_SHADER_GEOMETRY)
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return true;
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if (nir->info.stage == MESA_SHADER_TESS_EVAL &&
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!key.tes.as_es)
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return true;
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if (nir->info.stage == MESA_SHADER_VERTEX &&
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!key.vs.as_es && !key.vs.as_ls)
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return true;
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return false;
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}
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extern "C"
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bool r600_lower_to_scalar_instr_filter(const nir_instr *instr, const void *)
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{
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@ -618,6 +715,9 @@ int r600_shader_from_nir(struct r600_context *rctx,
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auto sh = nir_shader_clone(sel->nir, sel->nir);
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if (r600_is_last_vertex_stage(sh, *key))
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r600_lower_clipvertex_to_clipdist(sh, sel->so);
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if (sh->info.stage == MESA_SHADER_TESS_CTRL ||
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sh->info.stage == MESA_SHADER_TESS_EVAL ||
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(sh->info.stage == MESA_SHADER_VERTEX && key->vs.as_ls)) {
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@ -645,7 +745,6 @@ int r600_shader_from_nir(struct r600_context *rctx,
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NIR_PASS_V(sh, nir_lower_ubo_vec4);
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if (lower_64bit)
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NIR_PASS_V(sh, r600::r600_nir_64_to_vec2);
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@ -67,6 +67,8 @@ bool r600_merge_vec2_stores(nir_shader *shader);
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bool r600_split_64bit_uniforms_and_ubo(nir_shader *sh);
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bool r600_lower_64bit_to_vec2(nir_shader *sh);
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bool r600_split_64bit_alu_and_phi(nir_shader *sh);
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bool r600_lower_clipvertex_to_clipdist(nir_shader *sh);
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class AssemblyFromShader {
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public:
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@ -85,20 +85,26 @@ bool GeometryShader::process_store_output(nir_intrinsic_instr *instr)
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tgsi_semantic name = (tgsi_semantic)semantic.first;
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auto write_mask = nir_intrinsic_write_mask(instr);
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ShaderOutput output(driver_location, name, write_mask);
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output.set_sid(semantic.second);
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add_output(output);
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if (location == VARYING_SLOT_CLIP_DIST0 ||
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location == VARYING_SLOT_CLIP_DIST1) {
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m_clip_dist_mask |= 1 << (location - VARYING_SLOT_CLIP_DIST0);
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}
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if (!nir_intrinsic_io_semantics(instr).no_varying)
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output.set_sid(semantic.second);
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if (nir_intrinsic_io_semantics(instr).location != VARYING_SLOT_CLIP_VERTEX)
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add_output(output);
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if (location == VARYING_SLOT_VIEWPORT) {
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m_out_viewport = true;
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m_out_misc_write = true;
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}
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if (m_noutputs <= driver_location)
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if (location == VARYING_SLOT_CLIP_DIST0 ||
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location == VARYING_SLOT_CLIP_DIST1) {
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auto write_mask = nir_intrinsic_write_mask(instr);
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m_cc_dist_mask |= write_mask << (4 * (location - VARYING_SLOT_CLIP_DIST0));
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m_clip_dist_write |= write_mask << (4 * (location - VARYING_SLOT_CLIP_DIST0));
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}
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if (m_noutputs <= driver_location &&
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nir_intrinsic_io_semantics(instr).location != VARYING_SLOT_CLIP_VERTEX)
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m_noutputs = driver_location + 1;
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return true;
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@ -222,17 +228,17 @@ bool GeometryShader::emit_vertex(nir_intrinsic_instr* instr, bool cut)
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auto ir = new AluInstr(op2_add_int, m_export_base[stream], m_export_base[stream],
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value_factory().literal(m_noutputs),
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AluInstr::last_write);
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//ir->add_required_instr(cut_instr);
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emit_instruction(ir);
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}
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return true;
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}
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bool GeometryShader::store_output(nir_intrinsic_instr* instr)
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{
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if (nir_intrinsic_io_semantics(instr).location == VARYING_SLOT_CLIP_VERTEX)
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return true;
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auto location = nir_intrinsic_io_semantics(instr).location;
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auto index = nir_src_as_const_value(instr->src[1]);
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assert(index);
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@ -300,9 +306,6 @@ bool GeometryShader::store_output(nir_intrinsic_instr* instr)
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}
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}
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return true;
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}
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@ -347,6 +350,8 @@ void GeometryShader::do_get_shader_info(r600_shader *sh_info)
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{
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sh_info->processor_type = PIPE_SHADER_GEOMETRY;
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sh_info->ring_item_sizes[0] = m_ring_item_sizes[0];
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sh_info->cc_dist_mask = m_cc_dist_mask;
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sh_info->clip_dist_write = m_clip_dist_write;
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}
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bool GeometryShader::read_prop(std::istream& is)
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@ -50,7 +50,8 @@ private:
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bool m_first_vertex_emitted{false};
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int m_offset{0};
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int m_next_input_ring_offset{0};
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int m_clip_dist_mask{0};
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int m_cc_dist_mask{0};
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int m_clip_dist_write{0};
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int m_cur_ring_output{0};
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bool m_gs_tri_strip_adj_fix{false};
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uint64_t m_input_mask{0};
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@ -97,9 +97,13 @@ bool VertexExportForFs::do_store_output(const store_loc &store_info, nir_intrins
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case VARYING_SLOT_CLIP_VERTEX:
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return emit_clip_vertices(store_info, intr);
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case VARYING_SLOT_CLIP_DIST0:
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case VARYING_SLOT_CLIP_DIST1:
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case VARYING_SLOT_CLIP_DIST1: {
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bool success = emit_varying_pos(store_info, intr);
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m_num_clip_dist += 4;
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return emit_varying_param(store_info, intr) && emit_varying_pos(store_info, intr);
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if (!nir_intrinsic_io_semantics(&intr).no_varying)
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success &= emit_varying_param(store_info, intr);
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return success;
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}
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case VARYING_SLOT_LAYER: {
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m_out_misc_write = 1;
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m_vs_out_layer = 1;
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@ -128,29 +132,6 @@ bool VertexExportForFs::emit_clip_vertices(const store_loc &store_info, const ni
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m_output_registers[nir_intrinsic_base(&instr)] = &m_clip_vertex;
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RegisterVec4 clip_dist[2] = { vf.temp_vec4(pin_group), vf.temp_vec4(pin_group)};
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for (int i = 0; i < 8; i++) {
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int oreg = i >> 2;
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int ochan = i & 3;
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AluInstr *ir = nullptr;
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AluInstr::SrcValues src(8);
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for (int j = 0; j < 4; j++) {
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src[2 * j] = m_clip_vertex[j];
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src[2 * j + 1] = vf.uniform(512 + i, j, R600_BUFFER_INFO_CONST_BUFFER);
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}
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ir = new AluInstr(op2_dot4_ieee, clip_dist[oreg][ochan], src, AluInstr::last_write, 4);
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m_parent->emit_instruction(ir);
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}
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m_last_pos_export = new ExportInstr(ExportInstr::pos, m_cur_clip_pos++, clip_dist[0]);
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m_parent->emit_instruction(m_last_pos_export);
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m_last_pos_export = new ExportInstr(ExportInstr::pos, m_cur_clip_pos++, clip_dist[1]);
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m_parent->emit_instruction(m_last_pos_export);
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return true;
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}
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@ -450,22 +431,24 @@ bool VertexShader::do_scan_instruction(nir_instr *instr)
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output.set_sid(sid);
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switch (location) {
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case VARYING_SLOT_PSIZ:
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case VARYING_SLOT_POS:
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case VARYING_SLOT_CLIP_VERTEX:
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case VARYING_SLOT_EDGE: {
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break;
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}
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case VARYING_SLOT_CLIP_DIST0:
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case VARYING_SLOT_CLIP_DIST1:
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if (nir_intrinsic_io_semantics(intr).no_varying)
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break;
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FALLTHROUGH;
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case VARYING_SLOT_VIEWPORT:
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case VARYING_SLOT_LAYER:
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case VARYING_SLOT_VIEW_INDEX:
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default:
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output.set_is_param(true);
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FALLTHROUGH;
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case VARYING_SLOT_PSIZ:
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case VARYING_SLOT_POS:
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case VARYING_SLOT_CLIP_VERTEX:
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case VARYING_SLOT_EDGE:
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add_output(output);
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break;
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}
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add_output(output);
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break;
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}
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case nir_intrinsic_load_vertex_id:
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m_sv_values.set(es_vertexid);
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