From 32d67923b28e55cfe23883510509644e788003f0 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Thu, 1 Sep 2016 21:36:59 -0700 Subject: [PATCH] i965/fs: Fix LOAD_PAYLOAD handling in register coalesce is_nop_mov(). is_nop_mov() was broken for LOAD_PAYLOAD instructions in two ways: On the one hand the original destination register offset wasn't being taken into account which would give incorrect results if it was already non-zero, and on the other hand all source registers were being treated as if they had a size of 32B, which is almost never the case in SIMD16 programs for non-header sources. Reviewed-by: Iago Toral Quiroga --- src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp b/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp index 310e8019fcb..694cc0b0dd4 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp @@ -50,10 +50,12 @@ is_nop_mov(const fs_inst *inst) if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) { fs_reg dst = inst->dst; for (int i = 0; i < inst->sources; i++) { - dst.offset = i * REG_SIZE + dst.offset % REG_SIZE; if (!dst.equals(inst->src[i])) { return false; } + dst.offset += (i < inst->header_size ? REG_SIZE : + inst->exec_size * dst.stride * + type_sz(inst->src[i].type)); } return true; } else if (inst->opcode == BRW_OPCODE_MOV) {