freedreno/ir3: move VS driver-param emit
Move DP emit to it's own function. No functional change, just code motion to prepare for splitting up const state into multiple state- objs on a6xx. Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Rob Clark
parent
5722149bf1
commit
32014afa44
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@ -502,6 +502,87 @@ emit_common_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *rin
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}
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}
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void
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ir3_emit_vs_driver_params(const struct ir3_shader_variant *v,
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struct fd_ringbuffer *ring, struct fd_context *ctx,
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const struct pipe_draw_info *info)
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{
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debug_assert(ir3_needs_vs_driver_params(v));
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const struct ir3_const_state *const_state = &v->shader->const_state;
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uint32_t offset = const_state->offsets.driver_param;
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uint32_t vertex_params[IR3_DP_VS_COUNT] = {
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[IR3_DP_VTXID_BASE] = info->index_size ?
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info->index_bias : info->start,
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[IR3_DP_VTXCNT_MAX] = max_tf_vtx(ctx, v),
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};
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/* if no user-clip-planes, we don't need to emit the
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* entire thing:
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*/
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uint32_t vertex_params_size = 4;
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if (v->key.ucp_enables) {
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struct pipe_clip_state *ucp = &ctx->ucp;
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unsigned pos = IR3_DP_UCP0_X;
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for (unsigned i = 0; pos <= IR3_DP_UCP7_W; i++) {
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for (unsigned j = 0; j < 4; j++) {
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vertex_params[pos] = fui(ucp->ucp[i][j]);
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pos++;
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}
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}
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vertex_params_size = ARRAY_SIZE(vertex_params);
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}
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ring_wfi(ctx->batch, ring);
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bool needs_vtxid_base =
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ir3_find_sysval_regid(v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) != regid(63, 0);
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/* for indirect draw, we need to copy VTXID_BASE from
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* indirect-draw parameters buffer.. which is annoying
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* and means we can't easily emit these consts in cmd
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* stream so need to copy them to bo.
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*/
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if (info->indirect && needs_vtxid_base) {
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struct pipe_draw_indirect_info *indirect = info->indirect;
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struct pipe_resource *vertex_params_rsc =
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pipe_buffer_create(&ctx->screen->base,
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PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM,
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vertex_params_size * 4);
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unsigned src_off = info->indirect->offset;;
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void *ptr;
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ptr = fd_bo_map(fd_resource(vertex_params_rsc)->bo);
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memcpy(ptr, vertex_params, vertex_params_size * 4);
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if (info->index_size) {
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/* indexed draw, index_bias is 4th field: */
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src_off += 3 * 4;
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} else {
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/* non-indexed draw, start is 3rd field: */
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src_off += 2 * 4;
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}
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/* copy index_bias or start from draw params: */
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ctx->mem_to_mem(ring, vertex_params_rsc, 0,
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indirect->buffer, src_off, 1);
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emit_const(ctx, ring, v, offset * 4, 0,
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vertex_params_size, NULL, vertex_params_rsc);
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pipe_resource_reference(&vertex_params_rsc, NULL);
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} else {
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emit_const(ctx, ring, v, offset * 4, 0,
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vertex_params_size, vertex_params, NULL);
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}
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/* if needed, emit stream-out buffer addresses: */
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if (vertex_params[IR3_DP_VTXCNT_MAX] > 0) {
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emit_tfbos(ctx, v, ring);
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}
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}
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void
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ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
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struct fd_context *ctx, const struct pipe_draw_info *info)
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@ -511,81 +592,8 @@ ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *rin
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emit_common_consts(v, ring, ctx, PIPE_SHADER_VERTEX);
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/* emit driver params every time: */
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if (info) {
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const struct ir3_const_state *const_state = &v->shader->const_state;
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uint32_t offset = const_state->offsets.driver_param;
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if (v->constlen > offset) {
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uint32_t vertex_params[IR3_DP_VS_COUNT] = {
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[IR3_DP_VTXID_BASE] = info->index_size ?
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info->index_bias : info->start,
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[IR3_DP_VTXCNT_MAX] = max_tf_vtx(ctx, v),
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};
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/* if no user-clip-planes, we don't need to emit the
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* entire thing:
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*/
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uint32_t vertex_params_size = 4;
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if (v->key.ucp_enables) {
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struct pipe_clip_state *ucp = &ctx->ucp;
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unsigned pos = IR3_DP_UCP0_X;
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for (unsigned i = 0; pos <= IR3_DP_UCP7_W; i++) {
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for (unsigned j = 0; j < 4; j++) {
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vertex_params[pos] = fui(ucp->ucp[i][j]);
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pos++;
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}
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}
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vertex_params_size = ARRAY_SIZE(vertex_params);
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}
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ring_wfi(ctx->batch, ring);
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bool needs_vtxid_base =
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ir3_find_sysval_regid(v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) != regid(63, 0);
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/* for indirect draw, we need to copy VTXID_BASE from
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* indirect-draw parameters buffer.. which is annoying
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* and means we can't easily emit these consts in cmd
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* stream so need to copy them to bo.
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*/
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if (info->indirect && needs_vtxid_base) {
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struct pipe_draw_indirect_info *indirect = info->indirect;
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struct pipe_resource *vertex_params_rsc =
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pipe_buffer_create(&ctx->screen->base,
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PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM,
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vertex_params_size * 4);
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unsigned src_off = info->indirect->offset;;
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void *ptr;
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ptr = fd_bo_map(fd_resource(vertex_params_rsc)->bo);
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memcpy(ptr, vertex_params, vertex_params_size * 4);
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if (info->index_size) {
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/* indexed draw, index_bias is 4th field: */
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src_off += 3 * 4;
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} else {
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/* non-indexed draw, start is 3rd field: */
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src_off += 2 * 4;
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}
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/* copy index_bias or start from draw params: */
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ctx->mem_to_mem(ring, vertex_params_rsc, 0,
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indirect->buffer, src_off, 1);
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emit_const(ctx, ring, v, offset * 4, 0,
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vertex_params_size, NULL, vertex_params_rsc);
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pipe_resource_reference(&vertex_params_rsc, NULL);
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} else {
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emit_const(ctx, ring, v, offset * 4, 0,
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vertex_params_size, vertex_params, NULL);
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}
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/* if needed, emit stream-out buffer addresses: */
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if (vertex_params[IR3_DP_VTXCNT_MAX] > 0) {
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emit_tfbos(ctx, v, ring);
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}
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}
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}
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if (info && ir3_needs_vs_driver_params(v))
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ir3_emit_vs_driver_params(v, ring, ctx, info);
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}
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void
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@ -46,6 +46,19 @@ struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
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struct fd_ringbuffer;
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struct fd_context;
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static inline bool
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ir3_needs_vs_driver_params(const struct ir3_shader_variant *v)
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{
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const struct ir3_const_state *const_state = &v->shader->const_state;
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uint32_t offset = const_state->offsets.driver_param;
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return v->constlen > offset;
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}
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void ir3_emit_vs_driver_params(const struct ir3_shader_variant *v,
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struct fd_ringbuffer *ring, struct fd_context *ctx,
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const struct pipe_draw_info *info);
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void ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
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struct fd_context *ctx, const struct pipe_draw_info *info);
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void ir3_emit_fs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
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