freedreno/a5xx: set frag shader threadsize
Signed-off-by: Rob Clark <robdclark@gmail.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org>
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@ -336,11 +336,14 @@ fd5_program_emit(struct fd_ringbuffer *ring, struct fd5_emit *emit)
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uint32_t pos_regid, psize_regid, color_regid[8];
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uint32_t pos_regid, psize_regid, color_regid[8];
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uint32_t face_regid, coord_regid, zwcoord_regid;
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uint32_t face_regid, coord_regid, zwcoord_regid;
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uint32_t vcoord_regid, vertex_regid, instance_regid;
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uint32_t vcoord_regid, vertex_regid, instance_regid;
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enum a3xx_threadsize fssz;
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uint8_t psize_loc = ~0;
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uint8_t psize_loc = ~0;
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int i, j;
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int i, j;
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setup_stages(emit, s);
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setup_stages(emit, s);
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fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
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pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
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pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
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psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
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psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
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vertex_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID);
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vertex_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID);
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@ -554,7 +557,8 @@ fd5_program_emit(struct fd_ringbuffer *ring, struct fd5_emit *emit)
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}
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}
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OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 5);
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OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 5);
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OUT_RING(ring, 0x00000881); /* XXX HLSQ_CONTROL_0 */
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OUT_RING(ring, A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz) |
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0x00000880); /* XXX HLSQ_CONTROL_0 */
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OUT_RING(ring, A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(63));
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OUT_RING(ring, A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(63));
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OUT_RING(ring, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
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OUT_RING(ring, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
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0xfcfcfc00); /* XXX */
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0xfcfcfc00); /* XXX */
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@ -567,7 +571,8 @@ fd5_program_emit(struct fd_ringbuffer *ring, struct fd5_emit *emit)
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OUT_PKT4(ring, REG_A5XX_SP_FS_CTRL_REG0, 1);
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OUT_PKT4(ring, REG_A5XX_SP_FS_CTRL_REG0, 1);
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OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_SP_FS_CTRL_REG0_VARYING) |
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OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_SP_FS_CTRL_REG0_VARYING) |
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COND(s[FS].v->frag_coord, A5XX_SP_FS_CTRL_REG0_VARYING) |
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COND(s[FS].v->frag_coord, A5XX_SP_FS_CTRL_REG0_VARYING) |
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0x4000e | /* XXX set pretty much everywhere */
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0x40006 | /* XXX set pretty much everywhere */
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A5XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
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A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
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A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
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A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
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A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
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A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
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A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
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