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r600g: setup COLOR1 for possible dual-src in the framebuffer bind 

As pointed out by Marek, if we have only one cb, we may as well add this
single register write here rather than adding it in the draw loop.

Reviewed-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie 2012-04-27 09:38:46 +01:00
parent e253ead78e
commit 31a25dac98
4 changed files with 12 additions and 15 deletions
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8
src/gallium/drivers/r600/evergreen_state.c
View File

@ -1461,8 +1461,12 @@ static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rsta
}
rctx->alpha_ref_dirty = true;
if (cb == 0)
rctx->color0_format = color_info;
/* for possible dual-src MRT */
if (cb == 0 && rctx->framebuffer.nr_cbufs == 1) {
r600_pipe_state_add_reg_bo(rstate,
R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
color_info, &rtex->resource, RADEON_USAGE_READWRITE);
}
offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
offset >>= 8;

1
src/gallium/drivers/r600/r600_pipe.h
View File

@ -345,7 +345,6 @@ struct r600_context {
void *dummy_pixel_shader;
boolean dual_src_blend;
unsigned color0_format;
/* Vertex and index buffers. */
bool vertex_buffers_dirty;

8
src/gallium/drivers/r600/r600_state.c
View File

@ -1509,8 +1509,12 @@ static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
}
if (cb == 0)
rctx->color0_format = color_info;
/* for possible dual-src MRT write color info 1 */
if (cb == 0 && rctx->framebuffer.nr_cbufs == 1) {
r600_pipe_state_add_reg_bo(rstate,
R_0280A0_CB_COLOR0_INFO + 1 * 4,
color_info, &rtex->resource, RADEON_USAGE_READWRITE);
}
r600_pipe_state_add_reg_bo(rstate,
R_028040_CB_COLOR0_BASE + cb * 4,

10
src/gallium/drivers/r600/r600_state_common.c
View File

@ -806,11 +806,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control);
r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
if (rctx->chip_class <= R700)
r600_pipe_state_add_reg(&rctx->vgt, R_0280A4_CB_COLOR1_INFO, 0);
else
r600_pipe_state_add_reg(&rctx->vgt, 0x28CAC, 0);
}
rctx->vgt.nregs = 0;
@ -840,11 +835,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
rctx->vs_shader->shader.vs_prohibit_ucps ?
0 : rctx->rasterizer->clip_plane_enable & 0x3F));
if (rctx->dual_src_blend) {
r600_pipe_state_mod_reg(&rctx->vgt,
rctx->color0_format);
}
r600_context_pipe_state_set(rctx, &rctx->vgt);
/* Emit states (the function expects that we emit at most 17 dwords here). */