radeonsi: move default tess level constant buffer to RW buffers
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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302bec24bd
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3138a28ff2
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@ -1280,6 +1280,25 @@ static void declare_system_value(
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break;
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}
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case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
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case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
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{
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LLVMValueRef buf, slot, val[4];
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int i, offset;
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slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
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buf = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
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buf = build_indexed_load_const(ctx, buf, slot);
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offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
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for (i = 0; i < 4; i++)
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val[i] = buffer_load_const(gallivm->builder, buf,
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lp_build_const_int32(gallivm, (offset + i) * 4),
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ctx->f32);
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value = lp_build_gather_values(gallivm, val, 4);
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break;
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}
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case TGSI_SEMANTIC_PRIMID:
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value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
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break;
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@ -210,6 +210,12 @@ enum {
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SI_NUM_PARAMS = SI_PARAM_POS_FIXED_PT + 9, /* +8 for COLOR[0..1] */
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};
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/* SI-specific system values. */
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enum {
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TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI = TGSI_SEMANTIC_COUNT,
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TGSI_SEMANTIC_DEFAULT_TESSINNER_SI,
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};
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struct si_shader;
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/* A shader selector is a gallium CSO and contains shader variants and
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@ -3395,8 +3395,8 @@ static void si_set_tess_state(struct pipe_context *ctx,
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(void*)array, sizeof(array),
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&cb.buffer_offset);
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ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
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SI_DRIVER_STATE_CONST_BUF, &cb);
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si_set_constant_buffer(sctx, &sctx->rw_buffers,
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SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
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pipe_resource_reference(&cb.buffer, NULL);
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}
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@ -178,6 +178,7 @@ enum {
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SI_VS_STREAMOUT_BUF2,
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SI_VS_STREAMOUT_BUF3,
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SI_HS_CONST_DEFAULT_TESS_LEVELS,
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SI_VS_CONST_CLIP_PLANES,
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SI_PS_CONST_POLY_STIPPLE,
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SI_PS_CONST_SAMPLE_POSITIONS,
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@ -1804,7 +1804,7 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
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*/
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static void si_generate_fixed_func_tcs(struct si_context *sctx)
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{
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struct ureg_src const0, const1;
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struct ureg_src outer, inner;
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struct ureg_dst tessouter, tessinner;
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struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
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@ -1813,17 +1813,16 @@ static void si_generate_fixed_func_tcs(struct si_context *sctx)
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assert(!sctx->fixed_func_tcs_shader.cso);
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ureg_DECL_constant2D(ureg, 0, 1, SI_DRIVER_STATE_CONST_BUF);
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const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
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SI_DRIVER_STATE_CONST_BUF);
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const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
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SI_DRIVER_STATE_CONST_BUF);
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outer = ureg_DECL_system_value(ureg,
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TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
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inner = ureg_DECL_system_value(ureg,
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TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
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tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
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tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
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ureg_MOV(ureg, tessouter, const0);
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ureg_MOV(ureg, tessinner, const1);
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ureg_MOV(ureg, tessouter, outer);
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ureg_MOV(ureg, tessinner, inner);
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ureg_END(ureg);
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sctx->fixed_func_tcs_shader.cso =
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