i965/fs: Use the instruction execution size directly for texture generation
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
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@ -388,7 +388,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
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{
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int msg_type = -1;
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int rlen = 4;
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uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
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uint32_t simd_mode;
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uint32_t return_format;
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switch (dst.type) {
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@ -403,9 +403,16 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
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break;
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}
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if (dispatch_width == 16 &&
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!inst->force_uncompressed && !inst->force_sechalf)
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switch (inst->exec_size) {
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case 8:
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simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
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break;
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case 16:
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simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
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break;
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default:
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unreachable("Invalid width for texture instruction");
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}
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if (brw->gen >= 5) {
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switch (inst->opcode) {
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