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radeonsi: implement uncompressed MSAA texturing 

This is glBlitFramebuffer support for MSAA surfaces as required by GL 3.0
and texturing as required by GL 3.2 and GL_ARB_texture_multisample.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák 2013-07-30 22:29:30 +02:00
parent f083f79751
commit 2f1c449415
2 changed files with 13 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/gallium/drivers/radeonsi/radeonsi_pipe.c
View File

@ -368,7 +368,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
case PIPE_CAP_TGSI_INSTANCEID:
case PIPE_CAP_COMPUTE:
case PIPE_CAP_TEXTURE_MULTISAMPLE:
return 1;
case PIPE_CAP_TGSI_TEXCOORD:
return 0;
@ -390,7 +392,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_VERTEX_COLOR_CLAMPED:
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
case PIPE_CAP_USER_VERTEX_BUFFERS:
case PIPE_CAP_TEXTURE_MULTISAMPLE:
case PIPE_CAP_QUERY_TIMESTAMP:
case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
case PIPE_CAP_CUBE_MAP_ARRAY:

17
src/gallium/drivers/radeonsi/si_state.c
View File

@ -1555,7 +1555,7 @@ static unsigned si_tex_compare(unsigned compare)
}
}
static unsigned si_tex_dim(unsigned dim)
static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
{
switch (dim) {
default:
@ -1565,9 +1565,11 @@ static unsigned si_tex_dim(unsigned dim)
return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
case PIPE_TEXTURE_2D:
case PIPE_TEXTURE_RECT:
return V_008F1C_SQ_RSRC_IMG_2D;
return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
V_008F1C_SQ_RSRC_IMG_2D;
case PIPE_TEXTURE_2D_ARRAY:
return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
case PIPE_TEXTURE_3D:
return V_008F1C_SQ_RSRC_IMG_3D;
case PIPE_TEXTURE_CUBE:
@ -2653,11 +2655,14 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx
S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
0 : state->u.tex.first_level) |
S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
util_logbase2(texture->nr_samples) :
state->u.tex.last_level) |
S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
S_008F1C_POW2_PAD(texture->last_level > 0) |
S_008F1C_TYPE(si_tex_dim(texture->target)));
S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
S_008F24_LAST_ARRAY(state->u.tex.last_layer));