i965/fs: Indent the implementation of 32x32-bit MUL lowering by one level.
In order to make room for the code that will lower the MULH virtual instruction. Also move the hardware generation and execution type checks into the same branch, they are going to have to be different for MULH. Reviewed-by: Matt Turner <mattst88@gmail.com>
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@ -3129,21 +3129,24 @@ fs_visitor::lower_integer_multiplication()
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{
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bool progress = false;
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/* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit operation
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* directly, but CHV/BXT cannot.
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*/
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if (devinfo->gen >= 8 && !devinfo->is_cherryview && !devinfo->is_broxton)
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return false;
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foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
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if (inst->opcode != BRW_OPCODE_MUL ||
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inst->dst.is_accumulator() ||
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const fs_builder ibld(this, block, inst);
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if (inst->opcode == BRW_OPCODE_MUL) {
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if (inst->dst.is_accumulator() ||
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(inst->dst.type != BRW_REGISTER_TYPE_D &&
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inst->dst.type != BRW_REGISTER_TYPE_UD))
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continue;
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const fs_builder ibld(this, block, inst);
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/* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
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* operation directly, but CHV/BXT cannot.
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*/
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if (devinfo->gen >= 8 &&
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!devinfo->is_cherryview && !devinfo->is_broxton)
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continue;
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if (inst->src[1].file == IMM &&
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inst->src[1].fixed_hw_reg.dw1.ud < (1 << 16)) {
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/* The MUL instruction isn't commutative. On Gen <= 6, only the low
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* 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
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* src1 are used.
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@ -3151,8 +3154,6 @@ fs_visitor::lower_integer_multiplication()
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* If multiplying by an immediate value that fits in 16-bits, do a
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* single MUL instruction with that value in the proper location.
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*/
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if (inst->src[1].file == IMM &&
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inst->src[1].fixed_hw_reg.dw1.ud < (1 << 16)) {
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if (devinfo->gen < 7) {
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fs_reg imm(GRF, alloc.allocate(dispatch_width / 8),
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inst->dst.type);
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@ -3279,6 +3280,9 @@ fs_visitor::lower_integer_multiplication()
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ibld.MOV(null, inst->dst));
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}
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}
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} else {
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continue;
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}
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inst->remove(block);
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progress = true;
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