r300g: rename flag squaretiling -> drm_2_1_0
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e0b98cde41
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@ -889,7 +889,7 @@ struct pipe_resource *r300_texture_from_handle(struct pipe_screen *screen,
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break;
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case 2:
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if (rws->get_value(rws, R300_VID_SQUARE_TILING_SUPPORT))
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if (rws->get_value(rws, R300_VID_DRM_2_1_0))
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microtile = R300_BUFFER_SQUARETILED;
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break;
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}
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@ -361,7 +361,7 @@ static void r300_setup_tiling(struct r300_screen *screen,
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break;
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case 2:
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if (rws->get_value(rws, R300_VID_SQUARE_TILING_SUPPORT)) {
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if (rws->get_value(rws, R300_VID_DRM_2_1_0)) {
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desc->microtile = R300_BUFFER_SQUARETILED;
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}
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break;
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@ -50,7 +50,7 @@ enum r300_value_id {
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R300_VID_PCI_ID,
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R300_VID_GB_PIPES,
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R300_VID_Z_PIPES,
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R300_VID_SQUARE_TILING_SUPPORT,
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R300_VID_DRM_2_1_0, /* Square tiling. */
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R300_VID_DRM_2_3_0, /* R500 VAP regs, MSPOS regs, fixed tex3D size checking */
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R300_VID_DRM_2_6_0, /* Hyper-Z, GB_Z_PEQ_CONFIG on rv350->r4xx, R500 FG_ALPHA_VALUE */
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R300_VID_DRM_2_8_0, /* R500 US_FORMAT regs, R500 ARGB2101010 colorbuffer */
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@ -448,15 +448,18 @@ static void radeon_drm_buffer_set_tiling(struct r300_winsys_screen *ws,
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enum r300_buffer_tiling macrotiled,
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uint32_t pitch)
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{
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#ifndef RADEON_BO_FLAGS_MICRO_TILE_SQUARE
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#define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20
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#endif
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struct radeon_drm_buffer *buf = get_drm_buffer(radeon_pb_buffer(_buf));
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uint32_t flags = 0;
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if (microtiled == R300_BUFFER_TILED)
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flags |= RADEON_BO_FLAGS_MICRO_TILE;
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/* XXX Remove this ifdef when libdrm version 2.4.19 becomes mandatory. */
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#ifdef RADEON_BO_FLAGS_MICRO_TILE_SQUARE
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else if (microtiled == R300_BUFFER_SQUARETILED)
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flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE;
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#endif
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if (macrotiled == R300_BUFFER_TILED)
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flags |= RADEON_BO_FLAGS_MACRO_TILE;
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@ -107,12 +107,8 @@ static void do_ioctls(struct radeon_drm_winsys *winsys)
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exit(1);
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}
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/* XXX Remove this ifdef when libdrm version 2.4.19 becomes mandatory. */
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#ifdef RADEON_BO_FLAGS_MICRO_TILE_SQUARE
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// Supported since 2.1.0.
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winsys->squaretiling = version->version_major > 2 ||
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version->version_minor >= 1;
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#endif
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winsys->drm_2_1_0 = version->version_major > 2 ||
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version->version_minor >= 1;
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winsys->drm_2_3_0 = version->version_major > 2 ||
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version->version_minor >= 3;
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@ -145,8 +145,8 @@ static uint32_t radeon_get_value(struct r300_winsys_screen *rws,
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return ws->gb_pipes;
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case R300_VID_Z_PIPES:
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return ws->z_pipes;
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case R300_VID_SQUARE_TILING_SUPPORT:
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return ws->squaretiling;
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case R300_VID_DRM_2_1_0:
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return ws->drm_2_1_0;
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case R300_VID_DRM_2_3_0:
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return ws->drm_2_3_0;
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case R300_VID_DRM_2_6_0:
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@ -46,7 +46,7 @@ struct radeon_drm_winsys {
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uint32_t z_pipes; /* Z pipe count (rv530 only) */
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uint32_t gart_size; /* GART size. */
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uint32_t vram_size; /* VRAM size. */
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boolean squaretiling; /* Square tiling support. */
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boolean drm_2_1_0; /* Square tiling support. */
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/* DRM 2.3.0 (R500 VAP regs, MSPOS regs, fixed tex3D size checking) */
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boolean drm_2_3_0;
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/* DRM 2.6.0 (Hyper-Z, GB_Z_PEQ_CONFIG allowed on rv350->r4xx, FG_ALPHA_VALUE) */
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