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iris: utrace/perfetto support 

v2: Fixup gpu_id computation, use minor of /dev/dri/* % 128 since we
    don't know whether we get card0 or renderD128 for instance.
    (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com> (v1)
Acked-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13996>
This commit is contained in:
Lionel Landwerlin 2021-11-23 00:43:36 +02:00 committed by Marge Bot
parent 1d2fea6eae
commit 2e3490dd0f
15 changed files with 324 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
src/gallium/drivers/iris/iris_batch.c
View File

@ -41,11 +41,13 @@
#include "iris_bufmgr.h"
#include "iris_context.h"
#include "iris_fence.h"
#include "iris_utrace.h"
#include "drm-uapi/i915_drm.h"
#include "common/intel_aux_map.h"
#include "intel/common/intel_gem.h"
#include "intel/ds/intel_tracepoints.h"
#include "util/hash_table.h"
#include "util/set.h"
#include "util/u_upload_mgr.h"
@ -236,6 +238,8 @@ iris_init_batch(struct iris_context *ice,
iris_init_batch_measure(ice, batch);
u_trace_init(&batch->trace, &ice->ds.trace_context);
iris_batch_reset(batch);
}
@ -496,6 +500,8 @@ iris_batch_reset(struct iris_batch *batch)
struct iris_screen *screen = batch->screen;
struct iris_bufmgr *bufmgr = screen->bufmgr;
u_trace_fini(&batch->trace);
iris_bo_unreference(batch->bo);
batch->primary_batch_size = 0;
batch->total_chained_batch_size = 0;
@ -523,6 +529,9 @@ iris_batch_reset(struct iris_batch *batch)
add_bo_to_batch(batch, screen->workaround_bo, false);
iris_batch_maybe_noop(batch);
u_trace_init(&batch->trace, &batch->ice->ds.trace_context);
batch->begin_trace_recorded = false;
}
static void
@ -560,6 +569,8 @@ iris_batch_free(struct iris_batch *batch)
iris_destroy_batch_measure(batch->measure);
batch->measure = NULL;
u_trace_fini(&batch->trace);
_mesa_hash_table_destroy(batch->cache.render, NULL);
if (INTEL_DEBUG(DEBUG_ANY))
@ -678,6 +689,8 @@ iris_finish_batch(struct iris_batch *batch)
finish_seqno(batch);
trace_intel_end_batch(&batch->trace, batch, batch->name);
/* Emit MI_BATCH_BUFFER_END to finish our batch. */
uint32_t *map = batch->map_next;
@ -976,8 +989,8 @@ submit_batch(struct iris_batch *batch)
return ret;
}
static const char *
batch_name_to_string(enum iris_batch_name name)
const char *
iris_batch_name_to_string(enum iris_batch_name name)
{
const char *names[IRIS_BATCH_COUNT] = {
[IRIS_BATCH_RENDER] = "render",
@ -994,12 +1007,13 @@ void
_iris_batch_flush(struct iris_batch *batch, const char *file, int line)
{
struct iris_screen *screen = batch->screen;
struct iris_context *ice = batch->ice;
/* If a fence signals we need to flush it. */
if (iris_batch_bytes_used(batch) == 0 && !batch->contains_fence_signal)
return;
iris_measure_batch_end(batch->ice, batch);
iris_measure_batch_end(ice, batch);
iris_finish_batch(batch);
@ -1012,7 +1026,7 @@ _iris_batch_flush(struct iris_batch *batch, const char *file, int line)
fprintf(stderr, "%19s:%-3d: %s batch [%u] flush with %5db (%0.1f%%) "
"(cmds), %4d BOs (%0.1fMb aperture)\n",
file, line, batch_name_to_string(batch->name), batch->ctx_id,
file, line, iris_batch_name_to_string(batch->name), batch->ctx_id,
batch->total_chained_batch_size,
100.0f * batch->total_chained_batch_size / BATCH_SZ,
batch->exec_count,
@ -1020,7 +1034,10 @@ _iris_batch_flush(struct iris_batch *batch, const char *file, int line)
}
uint64_t start_ts = intel_ds_begin_submit(batch->ds);
uint64_t submission_id = batch->ds->submission_id;
int ret = submit_batch(batch);
intel_ds_end_submit(batch->ds, start_ts);
/* When batch submission fails, our end-of-batch syncobj remains
* unsignalled, and in fact is not even considered submitted.
@ -1052,6 +1069,9 @@ _iris_batch_flush(struct iris_batch *batch, const char *file, int line)
iris_bo_wait_rendering(batch->bo); /* if execbuf failed; this is a nop */
}
if (u_trace_context_actively_tracing(&ice->ds.trace_context))
iris_utrace_flush(batch, submission_id);
/* Start a new batch buffer. */
iris_batch_reset(batch);

20
src/gallium/drivers/iris/iris_batch.h
View File

@ -29,9 +29,12 @@
#include <string.h>
#include "util/u_dynarray.h"
#include "util/perf/u_trace.h"
#include "drm-uapi/i915_drm.h"
#include "common/intel_decoder.h"
#include "ds/intel_driver_ds.h"
#include "ds/intel_tracepoints.h"
#include "iris_fence.h"
#include "iris_fine_fence.h"
@ -96,6 +99,10 @@ struct iris_batch {
*/
bool noop_enabled;
/** Whether the first utrace point has been recorded.
*/
bool begin_trace_recorded;
/**
* A list of iris_syncobjs associated with this batch.
*
@ -176,6 +183,12 @@ struct iris_batch {
uint32_t last_aux_map_state;
struct iris_measure_batch *measure;
/** Where tracepoints are recorded */
struct u_trace trace;
/** Batch wrapper structure for perfetto */
struct intel_ds_queue *ds;
};
void iris_init_batches(struct iris_context *ice, int priority);
@ -229,6 +242,10 @@ iris_require_command_space(struct iris_batch *batch, unsigned size)
static inline void *
iris_get_command_space(struct iris_batch *batch, unsigned bytes)
{
if (!batch->begin_trace_recorded) {
batch->begin_trace_recorded = true;
trace_intel_begin_batch(&batch->trace, batch);
}
iris_require_command_space(batch, bytes);
void *map = batch->map_next;
batch->map_next += bytes;
@ -361,4 +378,7 @@ iris_batch_mark_reset_sync(struct iris_batch *batch)
batch->coherent_seqnos[i][j] = batch->next_seqno - 1;
}
const char *
iris_batch_name_to_string(enum iris_batch_name name);
#endif

11
src/gallium/drivers/iris/iris_blorp.c
View File

@ -403,6 +403,8 @@ blorp_measure_start(struct blorp_batch *blorp_batch,
struct iris_context *ice = blorp_batch->blorp->driver_ctx;
struct iris_batch *batch = blorp_batch->driver_batch;
trace_intel_begin_blorp(&batch->trace, batch);
if (batch->measure == NULL)
return;
@ -414,6 +416,15 @@ static void
blorp_measure_end(struct blorp_batch *blorp_batch,
const struct blorp_params *params)
{
struct iris_batch *batch = blorp_batch->driver_batch;
trace_intel_end_blorp(&batch->trace, batch,
params->x1 - params->x0,
params->y1 - params->y0,
params->hiz_op,
params->fast_clear_op,
params->shader_type,
params->shader_pipeline);
}
void

7
src/gallium/drivers/iris/iris_context.c
View File

@ -33,6 +33,7 @@
#include "iris_context.h"
#include "iris_resource.h"
#include "iris_screen.h"
#include "iris_utrace.h"
#include "common/intel_defines.h"
#include "common/intel_sample_positions.h"
@ -208,7 +209,6 @@ iris_flush_dirty_dmabufs(struct iris_context *ice)
clear_dirty_dmabuf_set(ice);
}
/**
* Destroy a context, freeing any associated memory.
*/
@ -243,6 +243,8 @@ iris_destroy_context(struct pipe_context *ctx)
iris_destroy_batches(ice);
iris_destroy_binder(&ice->state.binder);
iris_utrace_fini(ice);
slab_destroy_child(&ice->transfer_pool);
slab_destroy_child(&ice->transfer_pool_unsync);
@ -361,6 +363,9 @@ iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
if (INTEL_DEBUG(DEBUG_BATCH))
ice->state.sizes = _mesa_hash_table_u64_create(ice);
/* Do this before initializing the batches */
iris_utrace_init(ice);
iris_init_batches(ice, priority);
screen->vtbl.init_render_context(&ice->batches[IRIS_BATCH_RENDER]);

5
src/gallium/drivers/iris/iris_context.h
View File

@ -25,6 +25,7 @@
#include "pipe/p_context.h"
#include "pipe/p_state.h"
#include "util/perf/u_trace.h"
#include "util/set.h"
#include "util/slab.h"
#include "util/u_debug.h"
@ -33,6 +34,7 @@
#include "intel/dev/intel_debug.h"
#include "intel/common/intel_l3_config.h"
#include "intel/compiler/brw_compiler.h"
#include "intel/ds/intel_driver_ds.h"
#include "iris_batch.h"
#include "iris_binder.h"
#include "iris_fence.h"
@ -614,6 +616,8 @@ struct iris_context {
struct u_upload_mgr *query_buffer_uploader;
struct intel_ds_device ds;
struct {
struct {
/**
@ -890,6 +894,7 @@ void iris_copy_region(struct blorp_context *blorp,
unsigned src_level,
const struct pipe_box *src_box);
/* iris_draw.c */
void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info,

3
src/gallium/drivers/iris/iris_fence.c
View File

@ -271,6 +271,9 @@ iris_fence_flush(struct pipe_context *ctx,
iris_measure_frame_end(ice);
}
u_trace_context_process(&ice->ds.trace_context,
flags & PIPE_FLUSH_END_OF_FRAME);
if (!out_fence)
return;

2
src/gallium/drivers/iris/iris_screen.c
View File

@ -882,6 +882,8 @@ iris_screen_create(int fd, const struct pipe_screen_config *config)
glsl_type_singleton_init_or_ref();
intel_driver_ds_init();
/* FINISHME: Big core vs little core (for CPUs that have both kinds of
* cores) and, possibly, thread vs core should be considered here too.
*/

2
src/gallium/drivers/iris/iris_screen.h
View File

@ -45,6 +45,8 @@ struct iris_fs_prog_key;
struct iris_cs_prog_key;
enum iris_program_cache_id;
struct u_trace;
#define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
#define WRITE_ONCE(x, v) *(volatile __typeof__(x) *)&(x) = (v)

29
src/gallium/drivers/iris/iris_state.c
View File

@ -96,17 +96,20 @@
#include "util/u_upload_mgr.h"
#include "util/u_viewport.h"
#include "util/u_memory.h"
#include "util/u_trace_gallium.h"
#include "drm-uapi/i915_drm.h"
#include "nir.h"
#include "intel/compiler/brw_compiler.h"
#include "intel/common/intel_aux_map.h"
#include "intel/common/intel_l3_config.h"
#include "intel/common/intel_sample_positions.h"
#include "intel/ds/intel_tracepoints.h"
#include "iris_batch.h"
#include "iris_context.h"
#include "iris_defines.h"
#include "iris_pipe.h"
#include "iris_resource.h"
#include "iris_utrace.h"
#include "iris_genx_macros.h"
#include "intel/common/intel_guardband.h"
@ -5984,6 +5987,9 @@ iris_upload_dirty_render_state(struct iris_context *ice,
PIPE_CONTROL_STALL_AT_SCOREBOARD);
}
if (dirty & IRIS_DIRTY_RENDER_BUFFER)
trace_framebuffer_state(&batch->trace, batch, &ice->state.framebuffer);
for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
if (stage_dirty & (IRIS_STAGE_DIRTY_BINDINGS_VS << stage)) {
iris_populate_binding_table(ice, batch, stage, false);
@ -6756,6 +6762,8 @@ iris_upload_render_state(struct iris_context *ice,
{
bool use_predicate = ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT;
trace_intel_begin_draw(&batch->trace, batch);
if (ice->state.dirty & IRIS_DIRTY_VERTEX_BUFFER_FLUSHES)
flush_vbos(ice, batch);
@ -6990,6 +6998,8 @@ iris_upload_render_state(struct iris_context *ice,
}
iris_batch_sync_region_end(batch);
trace_intel_end_draw(&batch->trace, batch, 0);
}
static void
@ -7034,6 +7044,8 @@ iris_upload_compute_walker(struct iris_context *ice,
const struct brw_cs_dispatch_info dispatch =
brw_cs_get_dispatch_info(devinfo, cs_prog_data, grid->block);
trace_intel_begin_compute(&batch->trace, batch);
if (stage_dirty & IRIS_STAGE_DIRTY_CS) {
iris_emit_cmd(batch, GENX(CFE_STATE), cfe) {
cfe.MaximumNumberofThreads =
@ -7073,6 +7085,7 @@ iris_upload_compute_walker(struct iris_context *ice,
assert(brw_cs_push_const_total_size(cs_prog_data, dispatch.threads) == 0);
}
trace_intel_end_compute(&batch->trace, batch, grid->grid[0], grid->grid[1], grid->grid[2]);
}
#else /* #if GFX_VERx10 >= 125 */
@ -7096,6 +7109,8 @@ iris_upload_gpgpu_walker(struct iris_context *ice,
const struct brw_cs_dispatch_info dispatch =
brw_cs_get_dispatch_info(devinfo, cs_prog_data, grid->block);
trace_intel_begin_compute(&batch->trace, batch);
if ((stage_dirty & IRIS_STAGE_DIRTY_CS) ||
cs_prog_data->local_size[0] == 0 /* Variable local group size */) {
/* The MEDIA_VFE_STATE documentation for Gfx8+ says:
@ -7220,6 +7235,8 @@ iris_upload_gpgpu_walker(struct iris_context *ice,
}
iris_emit_cmd(batch, GENX(MEDIA_STATE_FLUSH), msf);
trace_intel_end_compute(&batch->trace, batch, grid->grid[0], grid->grid[1], grid->grid[2]);
}
#endif /* #if GFX_VERx10 >= 125 */
@ -7957,6 +7974,12 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
batch_mark_sync_for_pipe_control(batch, flags);
iris_batch_sync_region_start(batch);
const bool trace_pc =
(flags & (PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CACHE_INVALIDATE_BITS)) != 0;
if (trace_pc)
trace_intel_begin_stall(&batch->trace, batch);
iris_emit_cmd(batch, GENX(PIPE_CONTROL), pc) {
#if GFX_VERx10 >= 125
pc.PSSStallSyncEnable = flags & PIPE_CONTROL_PSS_STALL_SYNC;
@ -7998,6 +8021,12 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
pc.ImmediateData = imm;
}
if (trace_pc) {
trace_intel_end_stall(&batch->trace, batch, flags,
iris_utrace_pipe_flush_bit_to_ds_stall_flag,
reason);
}
iris_batch_sync_region_end(batch);
}

167
src/gallium/drivers/iris/iris_utrace.c Normal file
View File

@ -0,0 +1,167 @@
/*
* Copyright © 2021 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#include "iris_batch.h"
#include "iris_context.h"
#include "iris_utrace.h"
#include "util/u_trace_gallium.h"
#include "ds/intel_driver_ds.h"
#ifdef MAJOR_IN_MKDEV
#include <sys/mkdev.h>
#endif
#ifdef MAJOR_IN_SYSMACROS
#include <sys/sysmacros.h>
#endif
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
static void
iris_utrace_record_ts(struct u_trace *trace, void *_batch,
void *timestamps, unsigned idx,
bool end_of_pipe)
{
struct iris_batch *batch = _batch;
struct iris_resource *res = (void *) timestamps;
struct iris_bo *bo = res->bo;
iris_use_pinned_bo(batch, bo, true, IRIS_DOMAIN_NONE);
if (end_of_pipe) {
iris_emit_pipe_control_write(batch, "query: pipelined snapshot write",
PIPE_CONTROL_WRITE_TIMESTAMP,
bo, idx * sizeof(uint64_t), 0ull);
} else {
batch->screen->vtbl.store_register_mem64(batch,
0x2358,
bo, idx * sizeof(uint64_t),
false);
}
}
static uint64_t
iris_utrace_read_ts(struct u_trace_context *utctx,
void *timestamps, unsigned idx, void *flush_data)
{
struct iris_context *ice =
container_of(utctx, struct iris_context, ds.trace_context);
struct pipe_context *ctx = &ice->ctx;
struct iris_screen *screen = (struct iris_screen *)ctx->screen;
struct iris_resource *res = (void *) timestamps;
struct iris_bo *bo = res->bo;
if (idx == 0)
iris_bo_wait_rendering(bo);
uint64_t *ts = iris_bo_map(NULL, bo, MAP_READ);
/* Don't translate the no-timestamp marker: */
if (ts[idx] == U_TRACE_NO_TIMESTAMP)
return U_TRACE_NO_TIMESTAMP;
return intel_device_info_timebase_scale(&screen->devinfo, ts[idx]);
}
static void
iris_utrace_delete_flush_data(struct u_trace_context *utctx,
void *flush_data)
{
free(flush_data);
}
void iris_utrace_flush(struct iris_batch *batch, uint64_t submission_id)
{
struct intel_ds_flush_data *flush_data = malloc(sizeof(*flush_data));
intel_ds_flush_data_init(flush_data, batch->ds, submission_id);
u_trace_flush(&batch->trace, flush_data, false);
}
void iris_utrace_init(struct iris_context *ice)
{
struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
struct stat st;
uint32_t minor;
if (fstat(screen->fd, &st) == 0)
minor = minor(st.st_rdev);
else
minor = 0;
/* We could be dealing with /dev/dri/card0 or /dev/dri/renderD128 so to get
* a GPU ID we % 128 the minor number.
*/
intel_ds_device_init(&ice->ds, &screen->devinfo, screen->fd, minor % 128,
INTEL_DS_API_OPENGL);
u_trace_pipe_context_init(&ice->ds.trace_context, &ice->ctx,
iris_utrace_record_ts,
iris_utrace_read_ts,
iris_utrace_delete_flush_data);
for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
ice->batches[i].ds =
intel_ds_device_add_queue(&ice->ds, "%s",
iris_batch_name_to_string(i));
}
}
void iris_utrace_fini(struct iris_context *ice)
{
intel_ds_device_fini(&ice->ds);
}
enum intel_ds_stall_flag
iris_utrace_pipe_flush_bit_to_ds_stall_flag(uint32_t flags)
{
static const struct {
uint32_t iris;
enum intel_ds_stall_flag ds;
} iris_to_ds_flags[] = {
{ .iris = PIPE_CONTROL_DEPTH_CACHE_FLUSH, .ds = INTEL_DS_DEPTH_CACHE_FLUSH_BIT, },
{ .iris = PIPE_CONTROL_DATA_CACHE_FLUSH, .ds = INTEL_DS_DATA_CACHE_FLUSH_BIT, },
{ .iris = PIPE_CONTROL_TILE_CACHE_FLUSH, .ds = INTEL_DS_TILE_CACHE_FLUSH_BIT, },
{ .iris = PIPE_CONTROL_RENDER_TARGET_FLUSH, .ds = INTEL_DS_RENDER_TARGET_CACHE_FLUSH_BIT, },
{ .iris = PIPE_CONTROL_STATE_CACHE_INVALIDATE, .ds = INTEL_DS_STATE_CACHE_INVALIDATE_BIT, },
{ .iris = PIPE_CONTROL_CONST_CACHE_INVALIDATE, .ds = INTEL_DS_CONST_CACHE_INVALIDATE_BIT, },
{ .iris = PIPE_CONTROL_VF_CACHE_INVALIDATE, .ds = INTEL_DS_VF_CACHE_INVALIDATE_BIT, },
{ .iris = PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE, .ds = INTEL_DS_TEXTURE_CACHE_INVALIDATE_BIT, },
{ .iris = PIPE_CONTROL_INSTRUCTION_INVALIDATE, .ds = INTEL_DS_INST_CACHE_INVALIDATE_BIT, },
{ .iris = PIPE_CONTROL_DEPTH_STALL, .ds = INTEL_DS_DEPTH_STALL_BIT, },
{ .iris = PIPE_CONTROL_CS_STALL, .ds = INTEL_DS_CS_STALL_BIT, },
{ .iris = PIPE_CONTROL_FLUSH_HDC, .ds = INTEL_DS_HDC_PIPELINE_FLUSH_BIT, },
{ .iris = PIPE_CONTROL_STALL_AT_SCOREBOARD, .ds = INTEL_DS_STALL_AT_SCOREBOARD_BIT, },
};
enum intel_ds_stall_flag ret = 0;
for (uint32_t i = 0; i < ARRAY_SIZE(iris_to_ds_flags); i++) {
if (iris_to_ds_flags[i].iris & flags)
ret |= iris_to_ds_flags[i].ds;
}
assert(ret != 0);
return ret;
}

43
src/gallium/drivers/iris/iris_utrace.h Normal file
View File

@ -0,0 +1,43 @@
/*
* Copyright © 2021 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#ifndef IRIS_UTRACE_DOT_H
#define IRIS_UTRACE_DOT_H
#include <stdint.h>
enum intel_ds_stall_flag;
struct iris_context;
struct iris_batch;
void iris_utrace_init(struct iris_context *ice);
void iris_utrace_fini(struct iris_context *ice);
void iris_utrace_flush(struct iris_batch *batch,
uint64_t submission_id);
enum intel_ds_stall_flag
iris_utrace_pipe_flush_bit_to_ds_stall_flag(uint32_t flags);
#endif

7
src/gallium/drivers/iris/meson.build
View File

@ -55,6 +55,7 @@ files_libiris = files(
'iris_screen.c',
'iris_screen.h',
'iris_disk_cache.c',
'iris_utrace.c',
)
iris_per_hw_ver_libs = []
@ -68,7 +69,8 @@ foreach v : ['80', '90', '110', '120', '125']
'-DGFX_VERx10=@0@'.format(v),
],
gnu_symbol_visibility : 'hidden',
dependencies : [dep_libdrm, dep_valgrind, idep_genxml, idep_nir_headers],
dependencies : [dep_libdrm, dep_valgrind, idep_genxml, idep_nir_headers,
idep_intel_driver_ds_headers, ],
)
endforeach
@ -84,7 +86,8 @@ libiris = static_library(
c_args : [c_sse2_args],
cpp_args : [c_sse2_args],
gnu_symbol_visibility : 'hidden',
dependencies : [dep_libdrm, dep_valgrind, idep_genxml, idep_libintel_common, idep_nir_headers],
dependencies : [dep_libdrm, dep_valgrind, idep_genxml, idep_nir_headers,
idep_libintel_common, idep_intel_driver_ds, ],
link_with : [
iris_per_hw_ver_libs, libintel_compiler, libintel_dev, libisl,
libblorp, libintel_perf

1
src/intel/ds/intel_driver_ds.cc
View File

@ -403,6 +403,7 @@ extern "C" {
} \
CREATE_DUAL_EVENT_CALLBACK(batch, INTEL_DS_QUEUE_STAGE_CMD_BUFFER)
CREATE_DUAL_EVENT_CALLBACK(cmd_buffer, INTEL_DS_QUEUE_STAGE_CMD_BUFFER)
CREATE_DUAL_EVENT_CALLBACK(render_pass, INTEL_DS_QUEUE_STAGE_RENDER_PASS)
CREATE_DUAL_EVENT_CALLBACK(blorp, INTEL_DS_QUEUE_STAGE_BLORP)

5
src/intel/ds/intel_tracepoints.py
View File

@ -49,6 +49,11 @@ def define_tracepoints(args):
end_of_pipe=end_pipelined)
begin_end_tp('batch',
tp_args=[ArgStruct(type='uint8_t', var='name'),],
tp_struct=[Arg(type='uint8_t', name='name', var='name', c_format='%hhu'),],
end_pipelined=False)
begin_end_tp('cmd_buffer',
tp_args=[ArgStruct(type='uint8_t', var='level'),],
tp_struct=[Arg(type='uint8_t', name='level', var='level', c_format='%hhu'),],

1
src/intel/ds/meson.build
View File

@ -46,6 +46,7 @@ libintel_driver_ds = static_library(
idep_intel_driver_ds = declare_dependency(
link_with : libintel_driver_ds,
include_directories : [inc_include, inc_mapi, inc_mesa, inc_intel],
dependencies : idep_intel_driver_ds_headers,
)
if with_perfetto and (with_datasources.contains('intel') or with_datasources.contains('auto'))