radv: allow DCC for storage images on GFX10.3 with RADV_PERFTEST=dccstores
It's not enabled by default because it requires performance testing. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9919>
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@ -631,6 +631,8 @@ RADV driver environment variables
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enable wave32 for compute shaders (GFX10+)
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``dccmsaa``
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enable DCC for MSAA images
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``dccstores``
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enable DCC for storage images (for performance testing on GFX10.3 only)
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``dfsm``
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enable DFSM
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``gewave32``
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@ -76,6 +76,7 @@ enum {
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RADV_PERFTEST_DFSM = 1u << 7,
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RADV_PERFTEST_NO_SAM = 1u << 8,
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RADV_PERFTEST_SAM = 1u << 9,
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RADV_PERFTEST_DCC_STORES = 1u << 10,
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};
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bool
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@ -818,6 +818,7 @@ static const struct debug_control radv_perftest_options[] = {
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{"dfsm", RADV_PERFTEST_DFSM},
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{"nosam", RADV_PERFTEST_NO_SAM},
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{"sam", RADV_PERFTEST_SAM},
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{"dccstores", RADV_PERFTEST_DCC_STORES},
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{NULL, 0}
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};
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@ -294,7 +294,11 @@ bool radv_image_use_dcc_image_stores(const struct radv_device *device,
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*
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* DCC with MSAA > 2 samples results in CTS failures (some of dEQP-VK.pipeline.multisample.storage_image.*).
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*/
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return device->physical_device->rad_info.chip_class == GFX10 && image->info.samples <= 2;
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return (device->physical_device->rad_info.chip_class == GFX10 ||
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(device->physical_device->rad_info.chip_class == GFX10_3 &&
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(device->instance->perftest_flags & RADV_PERFTEST_DCC_STORES) &&
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!device->physical_device->use_llvm)) &&
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image->info.samples <= 2;
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}
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/*
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