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radv: allow DCC for storage images on GFX10.3 with RADV_PERFTEST=dccstores 

It's not enabled by default because it requires performance testing.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9919>
This commit is contained in:
Samuel Pitoiset 2021-03-30 14:50:58 +02:00 committed by Marge Bot
parent 65bca137bd
commit 2ded998a57
4 changed files with 9 additions and 1 deletions
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2
docs/envvars.rst
View File

@ -631,6 +631,8 @@ RADV driver environment variables
enable wave32 for compute shaders (GFX10+)
``dccmsaa``
enable DCC for MSAA images
``dccstores``
enable DCC for storage images (for performance testing on GFX10.3 only)
``dfsm``
enable DFSM
``gewave32``

1
src/amd/vulkan/radv_debug.h
View File

@ -76,6 +76,7 @@ enum {
RADV_PERFTEST_DFSM = 1u << 7,
RADV_PERFTEST_NO_SAM = 1u << 8,
RADV_PERFTEST_SAM = 1u << 9,
RADV_PERFTEST_DCC_STORES = 1u << 10,
};
bool

1
src/amd/vulkan/radv_device.c
View File

@ -818,6 +818,7 @@ static const struct debug_control radv_perftest_options[] = {
{"dfsm", RADV_PERFTEST_DFSM},
{"nosam", RADV_PERFTEST_NO_SAM},
{"sam", RADV_PERFTEST_SAM},
{"dccstores", RADV_PERFTEST_DCC_STORES},
{NULL, 0}
};

6
src/amd/vulkan/radv_image.c
View File

@ -294,7 +294,11 @@ bool radv_image_use_dcc_image_stores(const struct radv_device *device,
*
* DCC with MSAA > 2 samples results in CTS failures (some of dEQP-VK.pipeline.multisample.storage_image.*).
*/
return device->physical_device->rad_info.chip_class == GFX10 && image->info.samples <= 2;
return (device->physical_device->rad_info.chip_class == GFX10 ||
(device->physical_device->rad_info.chip_class == GFX10_3 &&
(device->instance->perftest_flags & RADV_PERFTEST_DCC_STORES) &&
!device->physical_device->use_llvm)) &&
image->info.samples <= 2;
}
/*