freedreno/drm-shim: Re-indent
clang-format -fallback-style=none --style=file -i src/freedreno/drm-shim/*.[ch] Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10293>
This commit is contained in:
Rob Clark
Marge Bot
parent
45856c5fbc
commit
2dbf09c2b4
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@ -24,35 +24,35 @@
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#include <limits.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <sys/ioctl.h>
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#include "drm-uapi/msm_drm.h"
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#include "drm-shim/drm_shim.h"
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#include "drm-uapi/msm_drm.h"
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#include <sys/ioctl.h>
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bool drm_shim_driver_prefers_first_render_node = true;
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struct msm_bo {
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struct shim_bo base;
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uint32_t offset;
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struct shim_bo base;
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uint32_t offset;
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};
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static struct msm_bo *
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msm_bo(struct shim_bo *bo)
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{
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return (struct msm_bo *)bo;
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return (struct msm_bo *)bo;
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}
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struct msm_device {
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uint32_t next_offset;
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uint32_t next_offset;
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};
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static struct msm_device msm = {
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.next_offset = 0x1000,
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.next_offset = 0x1000,
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};
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struct msm_device_info {
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uint32_t gpu_id;
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uint32_t chip_id;
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uint32_t gmem_size;
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uint32_t gpu_id;
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uint32_t chip_id;
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uint32_t gmem_size;
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};
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static const struct msm_device_info *device_info;
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@ -60,247 +60,246 @@ static const struct msm_device_info *device_info;
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static int
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msm_ioctl_noop(int fd, unsigned long request, void *arg)
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{
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return 0;
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return 0;
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}
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static int
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msm_ioctl_gem_new(int fd, unsigned long request, void *arg)
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{
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struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
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struct drm_msm_gem_new *create = arg;
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struct msm_bo *bo = calloc(1, sizeof(*bo));
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struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
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struct drm_msm_gem_new *create = arg;
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struct msm_bo *bo = calloc(1, sizeof(*bo));
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drm_shim_bo_init(&bo->base, create->size);
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drm_shim_bo_init(&bo->base, create->size);
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assert(UINT_MAX - msm.next_offset > create->size);
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assert(UINT_MAX - msm.next_offset > create->size);
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bo->offset = msm.next_offset;
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msm.next_offset += create->size;
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bo->offset = msm.next_offset;
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msm.next_offset += create->size;
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create->handle = drm_shim_bo_get_handle(shim_fd, &bo->base);
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create->handle = drm_shim_bo_get_handle(shim_fd, &bo->base);
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drm_shim_bo_put(&bo->base);
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drm_shim_bo_put(&bo->base);
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return 0;
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return 0;
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}
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static int
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msm_ioctl_gem_info(int fd, unsigned long request, void *arg)
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{
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struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
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struct drm_msm_gem_info *args = arg;
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struct shim_bo *bo = drm_shim_bo_lookup(shim_fd, args->handle);
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struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
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struct drm_msm_gem_info *args = arg;
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struct shim_bo *bo = drm_shim_bo_lookup(shim_fd, args->handle);
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switch (args->info) {
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case MSM_INFO_GET_OFFSET:
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args->value = drm_shim_bo_get_mmap_offset(shim_fd, bo);
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break;
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case MSM_INFO_GET_IOVA:
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args->value = msm_bo(bo)->offset;
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break;
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case MSM_INFO_SET_NAME:
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break;
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default:
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fprintf(stderr, "Unknown DRM_IOCTL_MSM_GEM_INFO %d\n", args->info);
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drm_shim_bo_put(bo);
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return -1;
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}
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switch (args->info) {
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case MSM_INFO_GET_OFFSET:
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args->value = drm_shim_bo_get_mmap_offset(shim_fd, bo);
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break;
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case MSM_INFO_GET_IOVA:
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args->value = msm_bo(bo)->offset;
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break;
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case MSM_INFO_SET_NAME:
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break;
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default:
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fprintf(stderr, "Unknown DRM_IOCTL_MSM_GEM_INFO %d\n", args->info);
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drm_shim_bo_put(bo);
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return -1;
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}
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drm_shim_bo_put(bo);
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drm_shim_bo_put(bo);
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return 0;
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return 0;
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}
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static int
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msm_ioctl_get_param(int fd, unsigned long request, void *arg)
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{
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struct drm_msm_param *gp = arg;
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struct drm_msm_param *gp = arg;
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switch (gp->param) {
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case MSM_PARAM_GPU_ID:
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gp->value = device_info->gpu_id;
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return 0;
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case MSM_PARAM_GMEM_SIZE:
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gp->value = device_info->gmem_size;
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return 0;
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case MSM_PARAM_GMEM_BASE:
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gp->value = 0x100000;
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return 0;
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case MSM_PARAM_CHIP_ID:
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gp->value = device_info->chip_id;
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return 0;
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case MSM_PARAM_NR_RINGS:
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gp->value = 1;
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return 0;
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case MSM_PARAM_MAX_FREQ:
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gp->value = 1000000;
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return 0;
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case MSM_PARAM_TIMESTAMP:
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gp->value = 0;
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return 0;
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case MSM_PARAM_PP_PGTABLE:
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gp->value = 1;
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return 0;
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case MSM_PARAM_FAULTS:
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gp->value = 0;
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return 0;
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default:
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fprintf(stderr, "Unknown DRM_IOCTL_MSM_GET_PARAM %d\n",
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gp->param);
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return -1;
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}
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switch (gp->param) {
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case MSM_PARAM_GPU_ID:
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gp->value = device_info->gpu_id;
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return 0;
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case MSM_PARAM_GMEM_SIZE:
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gp->value = device_info->gmem_size;
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return 0;
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case MSM_PARAM_GMEM_BASE:
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gp->value = 0x100000;
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return 0;
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case MSM_PARAM_CHIP_ID:
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gp->value = device_info->chip_id;
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return 0;
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case MSM_PARAM_NR_RINGS:
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gp->value = 1;
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return 0;
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case MSM_PARAM_MAX_FREQ:
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gp->value = 1000000;
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return 0;
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case MSM_PARAM_TIMESTAMP:
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gp->value = 0;
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return 0;
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case MSM_PARAM_PP_PGTABLE:
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gp->value = 1;
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return 0;
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case MSM_PARAM_FAULTS:
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gp->value = 0;
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return 0;
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default:
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fprintf(stderr, "Unknown DRM_IOCTL_MSM_GET_PARAM %d\n", gp->param);
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return -1;
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}
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}
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static int
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msm_ioctl_gem_madvise(int fd, unsigned long request, void *arg)
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{
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struct drm_msm_gem_madvise *args = arg;
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struct drm_msm_gem_madvise *args = arg;
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args->retained = true;
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args->retained = true;
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return 0;
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return 0;
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}
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static ioctl_fn_t driver_ioctls[] = {
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[DRM_MSM_GET_PARAM] = msm_ioctl_get_param,
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[DRM_MSM_GEM_NEW] = msm_ioctl_gem_new,
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[DRM_MSM_GEM_INFO] = msm_ioctl_gem_info,
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[DRM_MSM_GEM_CPU_PREP] = msm_ioctl_noop,
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[DRM_MSM_GEM_CPU_FINI] = msm_ioctl_noop,
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[DRM_MSM_GEM_SUBMIT] = msm_ioctl_noop,
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[DRM_MSM_WAIT_FENCE] = msm_ioctl_noop,
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[DRM_MSM_GEM_MADVISE] = msm_ioctl_gem_madvise,
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[DRM_MSM_SUBMITQUEUE_NEW] = msm_ioctl_noop,
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[DRM_MSM_SUBMITQUEUE_CLOSE] = msm_ioctl_noop,
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[DRM_MSM_SUBMITQUEUE_QUERY] = msm_ioctl_noop,
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[DRM_MSM_GET_PARAM] = msm_ioctl_get_param,
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[DRM_MSM_GEM_NEW] = msm_ioctl_gem_new,
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[DRM_MSM_GEM_INFO] = msm_ioctl_gem_info,
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[DRM_MSM_GEM_CPU_PREP] = msm_ioctl_noop,
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[DRM_MSM_GEM_CPU_FINI] = msm_ioctl_noop,
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[DRM_MSM_GEM_SUBMIT] = msm_ioctl_noop,
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[DRM_MSM_WAIT_FENCE] = msm_ioctl_noop,
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[DRM_MSM_GEM_MADVISE] = msm_ioctl_gem_madvise,
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[DRM_MSM_SUBMITQUEUE_NEW] = msm_ioctl_noop,
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[DRM_MSM_SUBMITQUEUE_CLOSE] = msm_ioctl_noop,
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[DRM_MSM_SUBMITQUEUE_QUERY] = msm_ioctl_noop,
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};
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#define CHIPID(maj, min, rev, pat) \
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((maj << 24) | (min << 16) | (rev << 8) | (pat))
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#define CHIPID(maj, min, rev, pat) \
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((maj << 24) | (min << 16) | (rev << 8) | (pat))
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static const struct msm_device_info device_infos[] = {
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{ /* First entry is default */
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.gpu_id = 630,
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.chip_id = CHIPID(6, 3, 0, 0xff),
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.gmem_size = 1024 * 1024,
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},
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{
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.gpu_id = 200,
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.chip_id = CHIPID(2, 0, 0, 0),
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.gmem_size = 256 * 1024,
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},
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{
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.gpu_id = 201,
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.chip_id = CHIPID(2, 0, 0, 1),
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.gmem_size = 128 * 1024,
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},
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{
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.gpu_id = 220,
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.chip_id = CHIPID(2, 2, 0, 0xff),
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.gmem_size = 512 * 1024,
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},
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{
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.gpu_id = 305,
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.chip_id = CHIPID(3, 0, 5, 0xff),
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.gmem_size = 256 * 1024,
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},
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{
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.gpu_id = 307,
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.chip_id = CHIPID(3, 0, 6, 0),
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.gmem_size = 128 * 1024,
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},
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{
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.gpu_id = 320,
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.chip_id = CHIPID(3, 2, 0xff, 0xff),
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.gmem_size = 512 * 1024,
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},
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{
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.gpu_id = 330,
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.chip_id = CHIPID(3, 3, 0, 0xff),
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.gmem_size = 1024 * 1024,
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},
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{
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.gpu_id = 420,
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.chip_id = CHIPID(4, 2, 0, 0xff),
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.gmem_size = 1536 * 1024,
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},
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{
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.gpu_id = 430,
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.chip_id = CHIPID(4, 3, 0, 0xff),
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.gmem_size = 1536 * 1024,
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},
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{
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.gpu_id = 510,
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.chip_id = CHIPID(5, 1, 0, 0xff),
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.gmem_size = 256 * 1024,
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},
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{
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.gpu_id = 530,
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.chip_id = CHIPID(5, 3, 0, 2),
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.gmem_size = 1024 * 1024,
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},
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{
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.gpu_id = 540,
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.chip_id = CHIPID(5, 4, 0, 2),
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.gmem_size = 1024 * 1024,
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},
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{
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.gpu_id = 618,
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.chip_id = CHIPID(6, 1, 8, 0xff),
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.gmem_size = 512 * 1024,
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},
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{
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.gpu_id = 630,
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.chip_id = CHIPID(6, 3, 0, 0xff),
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.gmem_size = 1024 * 1024,
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},
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{
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/* First entry is default */
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.gpu_id = 630,
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.chip_id = CHIPID(6, 3, 0, 0xff),
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.gmem_size = 1024 * 1024,
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},
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{
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.gpu_id = 200,
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.chip_id = CHIPID(2, 0, 0, 0),
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.gmem_size = 256 * 1024,
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},
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{
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.gpu_id = 201,
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.chip_id = CHIPID(2, 0, 0, 1),
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.gmem_size = 128 * 1024,
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},
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{
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.gpu_id = 220,
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.chip_id = CHIPID(2, 2, 0, 0xff),
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.gmem_size = 512 * 1024,
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},
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{
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.gpu_id = 305,
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.chip_id = CHIPID(3, 0, 5, 0xff),
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.gmem_size = 256 * 1024,
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},
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{
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.gpu_id = 307,
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.chip_id = CHIPID(3, 0, 6, 0),
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.gmem_size = 128 * 1024,
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},
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{
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.gpu_id = 320,
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.chip_id = CHIPID(3, 2, 0xff, 0xff),
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.gmem_size = 512 * 1024,
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},
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{
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.gpu_id = 330,
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.chip_id = CHIPID(3, 3, 0, 0xff),
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.gmem_size = 1024 * 1024,
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},
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{
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.gpu_id = 420,
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.chip_id = CHIPID(4, 2, 0, 0xff),
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.gmem_size = 1536 * 1024,
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},
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{
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.gpu_id = 430,
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.chip_id = CHIPID(4, 3, 0, 0xff),
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.gmem_size = 1536 * 1024,
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},
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{
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.gpu_id = 510,
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.chip_id = CHIPID(5, 1, 0, 0xff),
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.gmem_size = 256 * 1024,
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},
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{
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.gpu_id = 530,
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.chip_id = CHIPID(5, 3, 0, 2),
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.gmem_size = 1024 * 1024,
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},
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{
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.gpu_id = 540,
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.chip_id = CHIPID(5, 4, 0, 2),
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.gmem_size = 1024 * 1024,
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},
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{
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.gpu_id = 618,
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.chip_id = CHIPID(6, 1, 8, 0xff),
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.gmem_size = 512 * 1024,
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},
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{
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.gpu_id = 630,
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.chip_id = CHIPID(6, 3, 0, 0xff),
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.gmem_size = 1024 * 1024,
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},
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};
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static void
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msm_driver_get_device_info(void)
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{
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const char *env = getenv("FD_GPU_ID");
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const char *env = getenv("FD_GPU_ID");
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if (!env) {
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device_info = &device_infos[0];
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return;
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}
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if (!env) {
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device_info = &device_infos[0];
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return;
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}
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int gpu_id = atoi(env);
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for (int i = 0; i < ARRAY_SIZE(device_infos); i++) {
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if (device_infos[i].gpu_id == gpu_id) {
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device_info = &device_infos[i];
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return;
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}
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}
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int gpu_id = atoi(env);
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for (int i = 0; i < ARRAY_SIZE(device_infos); i++) {
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if (device_infos[i].gpu_id == gpu_id) {
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device_info = &device_infos[i];
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return;
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}
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}
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fprintf(stderr, "FD_GPU_ID unrecognized, shim supports %d",
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device_infos[0].gpu_id);
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for (int i = 1; i < ARRAY_SIZE(device_infos); i++)
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fprintf(stderr, ", %d", device_infos[i].gpu_id);
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fprintf(stderr, "\n");
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abort();
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fprintf(stderr, "FD_GPU_ID unrecognized, shim supports %d",
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device_infos[0].gpu_id);
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for (int i = 1; i < ARRAY_SIZE(device_infos); i++)
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fprintf(stderr, ", %d", device_infos[i].gpu_id);
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fprintf(stderr, "\n");
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abort();
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}
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void
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drm_shim_driver_init(void)
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{
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shim_device.bus_type = DRM_BUS_PLATFORM;
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shim_device.driver_name = "msm";
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shim_device.driver_ioctls = driver_ioctls;
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shim_device.driver_ioctl_count = ARRAY_SIZE(driver_ioctls);
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shim_device.bus_type = DRM_BUS_PLATFORM;
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shim_device.driver_name = "msm";
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shim_device.driver_ioctls = driver_ioctls;
|
||||
shim_device.driver_ioctl_count = ARRAY_SIZE(driver_ioctls);
|
||||
|
||||
/* msm uses the DRM version to expose features, instead of getparam. */
|
||||
shim_device.version_major = 1;
|
||||
shim_device.version_minor = 5;
|
||||
shim_device.version_patchlevel = 0;
|
||||
/* msm uses the DRM version to expose features, instead of getparam. */
|
||||
shim_device.version_major = 1;
|
||||
shim_device.version_minor = 5;
|
||||
shim_device.version_patchlevel = 0;
|
||||
|
||||
msm_driver_get_device_info();
|
||||
msm_driver_get_device_info();
|
||||
|
||||
drm_shim_override_file("OF_FULLNAME=/rdb/msm\n"
|
||||
"OF_COMPATIBLE_N=1\n"
|
||||
"OF_COMPATIBLE_0=qcom,adreno\n",
|
||||
"/sys/dev/char/%d:%d/device/uevent",
|
||||
DRM_MAJOR, render_node_minor);
|
||||
drm_shim_override_file("OF_FULLNAME=/rdb/msm\n"
|
||||
"OF_COMPATIBLE_N=1\n"
|
||||
"OF_COMPATIBLE_0=qcom,adreno\n",
|
||||
"/sys/dev/char/%d:%d/device/uevent", DRM_MAJOR,
|
||||
render_node_minor);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue