r600: work out target mask at framebuffer bind.
If we only get 1,2,3,6 framebuffers we want a sparse target mask. Reviewed-by: Roland Scheidegger <sroland@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -1436,7 +1436,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
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struct r600_surface *surf;
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struct r600_surface *surf;
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struct r600_texture *rtex;
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struct r600_texture *rtex;
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uint32_t i, log_samples;
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uint32_t i, log_samples;
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uint32_t target_mask = 0;
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/* Flush TC when changing the framebuffer state, because the only
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/* Flush TC when changing the framebuffer state, because the only
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* client not using TC that can change textures is the framebuffer.
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* client not using TC that can change textures is the framebuffer.
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* Other places don't typically have to flush TC.
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* Other places don't typically have to flush TC.
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@ -1463,6 +1463,8 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
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if (!surf)
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if (!surf)
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continue;
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continue;
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target_mask |= (0xf << (i * 4));
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rtex = (struct r600_texture*)surf->base.texture;
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rtex = (struct r600_texture*)surf->base.texture;
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r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
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r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
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@ -1528,7 +1530,9 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
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r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
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r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
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}
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}
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if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
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if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs ||
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rctx->cb_misc_state.bound_cbufs_target_mask != target_mask) {
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rctx->cb_misc_state.bound_cbufs_target_mask = target_mask;
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rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
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rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
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r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
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r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
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}
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}
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@ -2025,7 +2029,7 @@ static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_
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{
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{
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struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
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struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
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struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
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struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
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unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
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unsigned fb_colormask = a->bound_cbufs_target_mask;
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unsigned ps_colormask = a->ps_color_export_mask;
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unsigned ps_colormask = a->ps_color_export_mask;
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unsigned rat_colormask = evergreen_construct_rat_mask(rctx, a, a->nr_cbufs);
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unsigned rat_colormask = evergreen_construct_rat_mask(rctx, a, a->nr_cbufs);
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radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
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radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
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@ -152,6 +152,7 @@ struct r600_cb_misc_state {
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unsigned cb_color_control; /* this comes from blend state */
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unsigned cb_color_control; /* this comes from blend state */
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unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
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unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
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unsigned nr_cbufs;
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unsigned nr_cbufs;
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unsigned bound_cbufs_target_mask;
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unsigned nr_ps_color_outputs;
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unsigned nr_ps_color_outputs;
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unsigned ps_color_export_mask;
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unsigned ps_color_export_mask;
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unsigned image_rat_enabled_mask;
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unsigned image_rat_enabled_mask;
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@ -1525,7 +1525,7 @@ static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom
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}
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}
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radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
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radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
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} else {
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} else {
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unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
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unsigned fb_colormask = a->bound_cbufs_target_mask;
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unsigned ps_colormask = a->ps_color_export_mask;
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unsigned ps_colormask = a->ps_color_export_mask;
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unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
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unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
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