diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index 72b02a2cf0a..4e79cf56331 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -459,7 +459,10 @@ brw_miptree_layout_texture_3d(struct brw_context *brw, } void -brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt) +brw_miptree_layout(struct brw_context *brw, + bool for_bo, + enum intel_miptree_tiling_mode requested, + struct intel_mipmap_tree *mt) { bool multisampled = mt->num_samples > 1; bool gen6_hiz_or_stencil = false; @@ -543,6 +546,11 @@ brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt) DBG("%s: %dx%dx%d\n", __func__, mt->total_width, mt->total_height, mt->cpp); + if (!mt->total_width || !mt->total_height) { + intel_miptree_release(&mt); + return; + } + /* On Gen9+ the alignment values are expressed in multiples of the block * size */ @@ -552,5 +560,11 @@ brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt) mt->align_w /= i; mt->align_h /= j; } + + if (!for_bo) + mt->tiling = intel_miptree_choose_tiling(brw, mt->format, + mt->logical_width0, + mt->num_samples, + requested, mt); } diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 8616c0193c8..ef2f932272b 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -259,6 +259,7 @@ intel_miptree_create_layout(struct brw_context *brw, GLuint depth0, bool for_bo, GLuint num_samples, + enum intel_miptree_tiling_mode requested, bool force_all_slices_at_each_lod, bool disable_aux_buffers) { @@ -473,7 +474,7 @@ intel_miptree_create_layout(struct brw_context *brw, if (force_all_slices_at_each_lod) mt->array_layout = ALL_SLICES_AT_EACH_LOD; - brw_miptree_layout(brw, mt); + brw_miptree_layout(brw, for_bo, requested, mt); if (mt->disable_aux_buffers) assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS); @@ -484,7 +485,7 @@ intel_miptree_create_layout(struct brw_context *brw, /** * \brief Helper function for intel_miptree_create(). */ -static uint32_t +uint32_t intel_miptree_choose_tiling(struct brw_context *brw, mesa_format format, uint32_t width0, @@ -628,14 +629,14 @@ intel_lower_compressed_format(struct brw_context *brw, mesa_format format) struct intel_mipmap_tree * intel_miptree_create(struct brw_context *brw, - GLenum target, - mesa_format format, - GLuint first_level, - GLuint last_level, - GLuint width0, - GLuint height0, - GLuint depth0, - bool expect_accelerated_upload, + GLenum target, + mesa_format format, + GLuint first_level, + GLuint last_level, + GLuint width0, + GLuint height0, + GLuint depth0, + bool expect_accelerated_upload, GLuint num_samples, enum intel_miptree_tiling_mode requested_tiling, bool force_all_slices_at_each_lod) @@ -653,15 +654,12 @@ intel_miptree_create(struct brw_context *brw, first_level, last_level, width0, height0, depth0, false, num_samples, + requested_tiling, force_all_slices_at_each_lod, false /*disable_aux_buffers*/); - /* - * pitch == 0 || height == 0 indicates the null texture - */ - if (!mt || !mt->total_width || !mt->total_height) { - intel_miptree_release(&mt); + + if (!mt) return NULL; - } total_width = mt->total_width; total_height = mt->total_height; @@ -672,16 +670,11 @@ intel_miptree_create(struct brw_context *brw, total_height = ALIGN(total_height, 64); } - uint32_t tiling = intel_miptree_choose_tiling(brw, format, width0, - num_samples, requested_tiling, - mt); bool y_or_x = false; - if (tiling == (I915_TILING_Y | I915_TILING_X)) { + if (mt->tiling == (I915_TILING_Y | I915_TILING_X)) { y_or_x = true; mt->tiling = I915_TILING_Y; - } else { - mt->tiling = tiling; } unsigned long pitch; @@ -767,10 +760,18 @@ intel_miptree_create_for_bo(struct brw_context *brw, target = depth > 1 ? GL_TEXTURE_2D_ARRAY : GL_TEXTURE_2D; + /* 'requested' parameter of intel_miptree_create_layout() is relevant + * only for non bo miptree. Tiling for bo is already computed above. + * So, the tiling requested (INTEL_MIPTREE_TILING_ANY) below is + * just a place holder and will not make any change to the miptree + * tiling format. + */ mt = intel_miptree_create_layout(brw, target, format, 0, 0, width, height, depth, - true, 0, false, + true, 0, + INTEL_MIPTREE_TILING_ANY, + false, disable_aux_buffers); if (!mt) return NULL; diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 8b42e4adb79..1d51546abac 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -753,7 +753,11 @@ brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw, const struct intel_mipmap_tree *mt, unsigned level); -void brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt); +void +brw_miptree_layout(struct brw_context *brw, + bool for_bo, + enum intel_miptree_tiling_mode requested, + struct intel_mipmap_tree *mt); void *intel_miptree_map_raw(struct brw_context *brw, struct intel_mipmap_tree *mt); @@ -780,6 +784,14 @@ intel_miptree_unmap(struct brw_context *brw, unsigned int level, unsigned int slice); +uint32_t +intel_miptree_choose_tiling(struct brw_context *brw, + mesa_format format, + uint32_t width0, + uint32_t num_samples, + enum intel_miptree_tiling_mode requested, + struct intel_mipmap_tree *mt); + void intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, unsigned int level, unsigned int layer, enum gen6_hiz_op op);