s/0/NULL/ (Jeff Muizelaar)
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5c2f3d5d3a
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2c28dd892c
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@ -172,7 +172,7 @@ static const struct tnl_pipeline_stage *radeon_pipeline[] = {
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&_radeon_render_stage,
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&_tnl_render_stage, /* FALLBACK: */
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0,
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NULL,
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};
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@ -526,7 +526,7 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
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if (rmesa->state.scissor.pClipRects) {
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FREE(rmesa->state.scissor.pClipRects);
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rmesa->state.scissor.pClipRects = 0;
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rmesa->state.scissor.pClipRects = NULL;
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}
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if ( release_texture_heaps ) {
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@ -612,7 +612,7 @@ radeonMakeCurrent( __DRIcontextPrivate *driContextPriv,
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} else {
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if (RADEON_DEBUG & DEBUG_DRI)
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fprintf(stderr, "%s ctx is null\n", __FUNCTION__);
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_mesa_make_current( 0, 0 );
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_mesa_make_current( NULL, NULL );
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}
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if (RADEON_DEBUG & DEBUG_DRI)
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@ -301,7 +301,7 @@ void radeonFlushElts( radeonContextPtr rmesa )
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fprintf(stderr, "%s\n", __FUNCTION__);
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assert( rmesa->dma.flush == radeonFlushElts );
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rmesa->dma.flush = 0;
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rmesa->dma.flush = NULL;
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/* Cope with odd number of elts:
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*/
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@ -734,7 +734,7 @@ void radeonReleaseDmaRegion( radeonContextPtr rmesa,
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rmesa->dma.nr_released_bufs++;
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}
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region->buf = 0;
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region->buf = NULL;
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region->start = 0;
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}
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@ -389,7 +389,7 @@ static struct reg *lookup_reg( struct reg *tab, int reg )
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}
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fprintf(stderr, "*** unknown reg 0x%x\n", reg);
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return 0;
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return NULL;
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}
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@ -1808,7 +1808,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state )
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RADEON_STATECHANGE(rmesa, ctx );
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if ( state ) {
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rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_FOG_ENABLE;
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radeonFogfv( ctx, GL_FOG_MODE, 0 );
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radeonFogfv( ctx, GL_FOG_MODE, NULL );
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} else {
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rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_FOG_ENABLE;
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RADEON_STATECHANGE(rmesa, tcl);
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@ -529,8 +529,8 @@ void radeonInitState( radeonContextPtr rmesa )
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ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
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ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
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ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
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ctx->Driver.Lightfv( ctx, p, GL_POSITION, 0 );
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ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, 0 );
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ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
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ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
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ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
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ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
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ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
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@ -551,12 +551,12 @@ void radeonInitState( radeonContextPtr rmesa )
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ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
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}
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ctx->Driver.Fogfv( ctx, GL_FOG_MODE, 0 );
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ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
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ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
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ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
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ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
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ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
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ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, 0 );
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ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
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rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
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rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
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@ -365,7 +365,7 @@ static void flush_last_swtcl_prim( radeonContextPtr rmesa )
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if (RADEON_DEBUG & DEBUG_IOCTL)
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fprintf(stderr, "%s\n", __FUNCTION__);
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rmesa->dma.flush = 0;
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rmesa->dma.flush = NULL;
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if (rmesa->dma.current.buf) {
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struct radeon_dma_region *current = &rmesa->dma.current;
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@ -669,7 +669,7 @@ const struct tnl_pipeline_stage _radeon_render_stage =
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0, /* re-run (always runs) */
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GL_TRUE, /* active */
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0, 0, /* inputs (set in check_render), outputs */
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0, 0, /* changed_inputs, private */
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0, NULL, /* changed_inputs, private */
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dtr, /* destructor */
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radeon_check_render, /* check - initially set to alloc data */
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radeon_run_render /* run */
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@ -782,7 +782,7 @@ static void free_texrect_data( struct tnl_pipeline_stage *stage )
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if (store->texcoord[i].data)
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_mesa_vector4f_free( &store->texcoord[i] );
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FREE( store );
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stage->privatePtr = 0;
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stage->privatePtr = NULL;
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}
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}
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@ -1221,7 +1221,7 @@ void radeonDestroySwtcl( GLcontext *ctx )
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if (rmesa->swtcl.verts) {
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ALIGN_FREE(rmesa->swtcl.verts);
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rmesa->swtcl.verts = 0;
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rmesa->swtcl.verts = NULL;
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}
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}
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@ -405,7 +405,7 @@ const struct tnl_pipeline_stage _radeon_tcl_stage =
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0, /* re-run (always runs) */
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GL_TRUE, /* active */
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0, 0, /* inputs (set in check_render), outputs */
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0, 0, /* changed_inputs, private */
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0, NULL, /* changed_inputs, private */
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dtr, /* destructor */
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radeon_init_tcl_render, /* check - initially set to alloc data */
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radeon_run_tcl_render /* run */
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@ -472,7 +472,7 @@ static void transition_to_hwtnl( GLcontext *ctx )
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if ( rmesa->dma.flush )
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rmesa->dma.flush( rmesa );
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rmesa->dma.flush = 0;
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rmesa->dma.flush = NULL;
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rmesa->swtcl.vertex_format = 0;
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if (rmesa->swtcl.indexed_verts.buf)
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@ -178,7 +178,7 @@ static void flush_prims( radeonContextPtr rmesa )
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rmesa->tcl.vertex_format = rmesa->vb.vertex_format;
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rmesa->tcl.aos_components[0] = &tmp;
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rmesa->tcl.nr_aos_components = 1;
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rmesa->dma.flush = 0;
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rmesa->dma.flush = NULL;
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/* Optimize the primitive list:
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*/
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@ -602,7 +602,7 @@ static struct dynfn *lookup( struct dynfn *l, int key )
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return f;
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}
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return 0;
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return NULL;
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}
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/* Can't use the loopback template for this:
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@ -876,7 +876,7 @@ void radeonVtxfmtInitChoosers( GLvertexformat *vfmt )
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static struct dynfn *codegen_noop( GLcontext *ctx, int key )
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{
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(void) ctx; (void) key;
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return 0;
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return NULL;
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}
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void radeonInitCodegen( struct dfn_generators *gen, GLboolean useCodegen )
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@ -131,7 +131,7 @@ static struct dynfn *radeon_makeSSENormal3f( GLcontext *ctx, int key )
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static struct dynfn *radeon_makeSSEColor3fv( GLcontext *ctx, int key )
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{
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if (key & (RADEON_CP_VC_FRMT_PKCOLOR|RADEON_CP_VC_FRMT_FPALPHA))
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return 0;
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return NULL;
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else
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{
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radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
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@ -144,7 +144,7 @@ static struct dynfn *radeon_makeSSEColor3fv( GLcontext *ctx, int key )
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static struct dynfn *radeon_makeSSEColor3f( GLcontext *ctx, int key )
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{
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if (key & (RADEON_CP_VC_FRMT_PKCOLOR|RADEON_CP_VC_FRMT_FPALPHA))
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return 0;
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return NULL;
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else
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{
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radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
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@ -303,14 +303,14 @@ struct dynfn *radeon_makeX86Color4ub( GLcontext *ctx, int key )
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return dfn;
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}
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else
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return 0;
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return NULL;
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}
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struct dynfn *radeon_makeX86Color3fv( GLcontext *ctx, int key )
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{
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if (key & (RADEON_CP_VC_FRMT_PKCOLOR|RADEON_CP_VC_FRMT_FPALPHA))
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return 0;
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return NULL;
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else
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{
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radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
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@ -323,7 +323,7 @@ struct dynfn *radeon_makeX86Color3fv( GLcontext *ctx, int key )
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struct dynfn *radeon_makeX86Color3f( GLcontext *ctx, int key )
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{
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if (key & (RADEON_CP_VC_FRMT_PKCOLOR|RADEON_CP_VC_FRMT_FPALPHA))
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return 0;
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return NULL;
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else
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{
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radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
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