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aco: Fix -Wshadow warnings 

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7430>
This commit is contained in:
Tony Wasserka 2020-11-03 14:40:05 +01:00 committed by Marge Bot
parent bc7f442d8e
commit 2bb8874320
16 changed files with 194 additions and 196 deletions
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10
src/amd/compiler/aco_assembler.cpp
View File

@ -18,7 +18,7 @@ struct asm_context {
const int16_t* opcode; const int16_t* opcode;
// TODO: keep track of branch instructions referring blocks // TODO: keep track of branch instructions referring blocks
// and, when emitting the block, correct the offset in instr // and, when emitting the block, correct the offset in instr
asm_context(Program* program) : program(program), chip_class(program->chip_class) { asm_context(Program* program_) : program(program_), chip_class(program->chip_class) {
if (chip_class <= GFX7) if (chip_class <= GFX7)
opcode = &instr_info.opcode_gfx7[0]; opcode = &instr_info.opcode_gfx7[0];
else if (chip_class <= GFX9) else if (chip_class <= GFX9)
@ -82,18 +82,18 @@ void emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction*
uint32_t opcode = ctx.opcode[(int)instr->opcode]; uint32_t opcode = ctx.opcode[(int)instr->opcode];
if (opcode == (uint32_t)-1) { if (opcode == (uint32_t)-1) {
char *out; char *outmem;
size_t outsize; size_t outsize;
struct u_memstream mem; struct u_memstream mem;
u_memstream_open(&mem, &out, &outsize); u_memstream_open(&mem, &outmem, &outsize);
FILE *const memf = u_memstream_get(&mem); FILE *const memf = u_memstream_get(&mem);
fprintf(memf, "Unsupported opcode: "); fprintf(memf, "Unsupported opcode: ");
aco_print_instr(instr, memf); aco_print_instr(instr, memf);
u_memstream_close(&mem); u_memstream_close(&mem);
aco_err(ctx.program, out); aco_err(ctx.program, outmem);
free(out); free(outmem);
abort(); abort();
} }

2
src/amd/compiler/aco_builder_h.py
View File

@ -117,7 +117,7 @@ public:
struct Result { struct Result {
Instruction *instr; Instruction *instr;
Result(Instruction *instr) : instr(instr) {} Result(Instruction *instr_) : instr(instr_) {}
operator Instruction *() const { operator Instruction *() const {
return instr; return instr;

45
src/amd/compiler/aco_insert_exec_mask.cpp
View File

@ -55,7 +55,7 @@ struct wqm_ctx {
std::vector<bool> branch_wqm; /* true if the branch condition in this block should be in wqm */ std::vector<bool> branch_wqm; /* true if the branch condition in this block should be in wqm */
bool loop; bool loop;
bool wqm; bool wqm;
wqm_ctx(Program* program) : program(program), wqm_ctx(Program* program_) : program(program_),
defined_in(program->peekAllocationId(), 0xFFFF), defined_in(program->peekAllocationId(), 0xFFFF),
needs_wqm(program->peekAllocationId()), needs_wqm(program->peekAllocationId()),
branch_wqm(program->blocks.size()), branch_wqm(program->blocks.size()),
@ -74,8 +74,8 @@ struct loop_info {
bool has_divergent_break; bool has_divergent_break;
bool has_divergent_continue; bool has_divergent_continue;
bool has_discard; /* has a discard or demote */ bool has_discard; /* has a discard or demote */
loop_info(Block* b, uint16_t num, uint8_t needs, bool breaks, bool cont, bool discard) : loop_info(Block* b, uint16_t num, uint8_t needs_, bool breaks, bool cont, bool discard) :
loop_header(b), num_exec_masks(num), needs(needs), has_divergent_break(breaks), loop_header(b), num_exec_masks(num), needs(needs_), has_divergent_break(breaks),
has_divergent_continue(cont), has_discard(discard) {} has_divergent_continue(cont), has_discard(discard) {}
}; };
@ -93,7 +93,7 @@ struct exec_ctx {
std::vector<block_info> info; std::vector<block_info> info;
std::vector<loop_info> loop; std::vector<loop_info> loop;
bool handle_wqm = false; bool handle_wqm = false;
exec_ctx(Program *program) : program(program), info(program->blocks.size()) {} exec_ctx(Program *program_) : program(program_), info(program->blocks.size()) {}
}; };
bool pred_by_exec_mask(aco_ptr<Instruction>& instr) { bool pred_by_exec_mask(aco_ptr<Instruction>& instr) {
@ -475,23 +475,26 @@ unsigned add_coupling_code(exec_ctx& ctx, Block* block,
/* fill the loop header phis */ /* fill the loop header phis */
std::vector<unsigned>& header_preds = header->linear_preds; std::vector<unsigned>& header_preds = header->linear_preds;
int k = 0; int instr_idx = 0;
if (info.has_discard) { if (info.has_discard) {
while (k < info.num_exec_masks - 1) { while (instr_idx < info.num_exec_masks - 1) {
aco_ptr<Instruction>& phi = header->instructions[k]; aco_ptr<Instruction>& phi = header->instructions[instr_idx];
assert(phi->opcode == aco_opcode::p_linear_phi); assert(phi->opcode == aco_opcode::p_linear_phi);
for (unsigned i = 1; i < phi->operands.size(); i++) for (unsigned i = 1; i < phi->operands.size(); i++)
phi->operands[i] = Operand(ctx.info[header_preds[i]].exec[k].first); phi->operands[i] = Operand(ctx.info[header_preds[i]].exec[instr_idx].first);
k++; instr_idx++;
} }
} }
aco_ptr<Instruction>& phi = header->instructions[k++];
assert(phi->opcode == aco_opcode::p_linear_phi); {
for (unsigned i = 1; i < phi->operands.size(); i++) aco_ptr<Instruction>& phi = header->instructions[instr_idx++];
phi->operands[i] = Operand(ctx.info[header_preds[i]].exec[info.num_exec_masks - 1].first); assert(phi->opcode == aco_opcode::p_linear_phi);
for (unsigned i = 1; i < phi->operands.size(); i++)
phi->operands[i] = Operand(ctx.info[header_preds[i]].exec[info.num_exec_masks - 1].first);
}
if (info.has_divergent_break) { if (info.has_divergent_break) {
aco_ptr<Instruction>& phi = header->instructions[k]; aco_ptr<Instruction>& phi = header->instructions[instr_idx];
assert(phi->opcode == aco_opcode::p_linear_phi); assert(phi->opcode == aco_opcode::p_linear_phi);
for (unsigned i = 1; i < phi->operands.size(); i++) for (unsigned i = 1; i < phi->operands.size(); i++)
phi->operands[i] = Operand(ctx.info[header_preds[i]].exec[info.num_exec_masks].first); phi->operands[i] = Operand(ctx.info[header_preds[i]].exec[info.num_exec_masks].first);
@ -501,17 +504,17 @@ unsigned add_coupling_code(exec_ctx& ctx, Block* block,
/* create the loop exit phis if not trivial */ /* create the loop exit phis if not trivial */
bool need_parallelcopy = false; bool need_parallelcopy = false;
for (unsigned k = 0; k < info.num_exec_masks; k++) { for (unsigned exec_idx = 0; exec_idx < info.num_exec_masks; exec_idx++) {
Temp same = ctx.info[preds[0]].exec[k].first; Temp same = ctx.info[preds[0]].exec[exec_idx].first;
uint8_t type = ctx.info[header_preds[0]].exec[k].second; uint8_t type = ctx.info[header_preds[0]].exec[exec_idx].second;
bool trivial = true; bool trivial = true;
for (unsigned i = 1; i < preds.size() && trivial; i++) { for (unsigned i = 1; i < preds.size() && trivial; i++) {
if (ctx.info[preds[i]].exec[k].first != same) if (ctx.info[preds[i]].exec[exec_idx].first != same)
trivial = false; trivial = false;
} }
if (k == info.num_exec_masks - 1u) { if (exec_idx == info.num_exec_masks - 1u) {
bool all_liveout_exec = true; bool all_liveout_exec = true;
bool all_not_liveout_exec = true; bool all_not_liveout_exec = true;
for (unsigned pred : preds) { for (unsigned pred : preds) {
@ -532,12 +535,12 @@ unsigned add_coupling_code(exec_ctx& ctx, Block* block,
/* create phi for loop footer */ /* create phi for loop footer */
aco_ptr<Pseudo_instruction> phi{create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, preds.size(), 1)}; aco_ptr<Pseudo_instruction> phi{create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, preds.size(), 1)};
phi->definitions[0] = bld.def(bld.lm); phi->definitions[0] = bld.def(bld.lm);
if (k == info.num_exec_masks - 1u) { if (exec_idx == info.num_exec_masks - 1u) {
phi->definitions[0].setFixed(exec); phi->definitions[0].setFixed(exec);
need_parallelcopy = false; need_parallelcopy = false;
} }
for (unsigned i = 0; i < phi->operands.size(); i++) for (unsigned i = 0; i < phi->operands.size(); i++)
phi->operands[i] = Operand(ctx.info[preds[i]].exec[k].first); phi->operands[i] = Operand(ctx.info[preds[i]].exec[exec_idx].first);
ctx.info[idx].exec.emplace_back(bld.insert(std::move(phi)), type); ctx.info[idx].exec.emplace_back(bld.insert(std::move(phi)), type);
} }
} }

6
src/amd/compiler/aco_insert_waitcnt.cpp
View File

@ -203,9 +203,9 @@ struct wait_entry {
bool has_vmem_nosampler:1; bool has_vmem_nosampler:1;
bool has_vmem_sampler:1; bool has_vmem_sampler:1;
wait_entry(wait_event event, wait_imm imm, bool logical, bool wait_on_read) wait_entry(wait_event event_, wait_imm imm_, bool logical_, bool wait_on_read_)
: imm(imm), events(event), counters(get_counters_for_event(event)), : imm(imm_), events(event_), counters(get_counters_for_event(event_)),
wait_on_read(wait_on_read), logical(logical), wait_on_read(wait_on_read_), logical(logical_),
has_vmem_nosampler(false), has_vmem_sampler(false) {} has_vmem_nosampler(false), has_vmem_sampler(false) {}
bool join(const wait_entry& other) bool join(const wait_entry& other)

83
src/amd/compiler/aco_instruction_selection.cpp
View File

@ -1579,15 +1579,15 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
src0, src1); src0, src1);
bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t) -1), tmp, bld.scc(carry)); bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t) -1), tmp, bld.scc(carry));
} else if (dst.regClass() == v2b) { } else if (dst.regClass() == v2b) {
Instruction *instr; Instruction *add_instr;
if (ctx->program->chip_class >= GFX10) { if (ctx->program->chip_class >= GFX10) {
instr = bld.vop3(aco_opcode::v_add_u16_e64, Definition(dst), src0, src1).instr; add_instr = bld.vop3(aco_opcode::v_add_u16_e64, Definition(dst), src0, src1).instr;
} else { } else {
if (src1.type() == RegType::sgpr) if (src1.type() == RegType::sgpr)
std::swap(src0, src1); std::swap(src0, src1);
instr = bld.vop2_e64(aco_opcode::v_add_u16, Definition(dst), src0, as_vgpr(ctx, src1)).instr; add_instr = bld.vop2_e64(aco_opcode::v_add_u16, Definition(dst), src0, as_vgpr(ctx, src1)).instr;
} }
static_cast<VOP3A_instruction*>(instr)->clamp = 1; static_cast<VOP3A_instruction*>(add_instr)->clamp = 1;
} else if (dst.regClass() == v1) { } else if (dst.regClass() == v1) {
if (ctx->options->chip_class >= GFX9) { if (ctx->options->chip_class >= GFX9) {
aco_ptr<VOP3A_instruction> add{create_instruction<VOP3A_instruction>(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)}; aco_ptr<VOP3A_instruction> add{create_instruction<VOP3A_instruction>(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)};
@ -3190,21 +3190,21 @@ void emit_load(isel_context *ctx, Builder &bld, const LoadEmitInfo &info,
/* shift result right if needed */ /* shift result right if needed */
if (params.byte_align_loads && info.component_size < 4) { if (params.byte_align_loads && info.component_size < 4) {
Operand align((uint32_t)byte_align); Operand byte_align_off((uint32_t)byte_align);
if (byte_align == -1) { if (byte_align == -1) {
if (offset.isConstant()) if (offset.isConstant())
align = Operand(offset.constantValue() % 4u); byte_align_off = Operand(offset.constantValue() % 4u);
else if (offset.size() == 2) else if (offset.size() == 2)
align = Operand(emit_extract_vector(ctx, offset.getTemp(), 0, RegClass(offset.getTemp().type(), 1))); byte_align_off = Operand(emit_extract_vector(ctx, offset.getTemp(), 0, RegClass(offset.getTemp().type(), 1)));
else else
align = offset; byte_align_off = offset;
} }
assert(val.bytes() >= load_size && "unimplemented"); assert(val.bytes() >= load_size && "unimplemented");
if (val.type() == RegType::sgpr) if (val.type() == RegType::sgpr)
byte_align_scalar(ctx, val, align, info.dst); byte_align_scalar(ctx, val, byte_align_off, info.dst);
else else
byte_align_vector(ctx, val, align, info.dst, component_size); byte_align_vector(ctx, val, byte_align_off, info.dst, component_size);
return; return;
} }
@ -3239,8 +3239,8 @@ void emit_load(isel_context *ctx, Builder &bld, const LoadEmitInfo &info,
if (num_tmps > 1) { if (num_tmps > 1) {
aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>( aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(
aco_opcode::p_create_vector, Format::PSEUDO, num_tmps, 1)}; aco_opcode::p_create_vector, Format::PSEUDO, num_tmps, 1)};
for (unsigned i = 0; i < num_tmps; i++) for (unsigned j = 0; j < num_tmps; j++)
vec->operands[i] = Operand(tmp[i]); vec->operands[j] = Operand(tmp[j]);
tmp[0] = bld.tmp(RegClass::get(reg_type, tmp_size)); tmp[0] = bld.tmp(RegClass::get(reg_type, tmp_size));
vec->definitions[0] = Definition(tmp[0]); vec->definitions[0] = Definition(tmp[0]);
bld.insert(std::move(vec)); bld.insert(std::move(vec));
@ -3263,10 +3263,10 @@ void emit_load(isel_context *ctx, Builder &bld, const LoadEmitInfo &info,
assert(tmp_size % elem_rc.bytes() == 0); assert(tmp_size % elem_rc.bytes() == 0);
aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>( aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(
aco_opcode::p_split_vector, Format::PSEUDO, 1, tmp_size / elem_rc.bytes())}; aco_opcode::p_split_vector, Format::PSEUDO, 1, tmp_size / elem_rc.bytes())};
for (unsigned i = 0; i < split->definitions.size(); i++) { for (auto& def : split->definitions) {
Temp component = bld.tmp(elem_rc); Temp component = bld.tmp(elem_rc);
allocated_vec[components_split++] = component; allocated_vec[components_split++] = component;
split->definitions[i] = Definition(component); def = Definition(component);
} }
split->operands[0] = Operand(tmp[0]); split->operands[0] = Operand(tmp[0]);
bld.insert(std::move(split)); bld.insert(std::move(split));
@ -3496,31 +3496,31 @@ Temp global_load_callback(Builder& bld, const LoadEmitInfo &info,
Temp dst_hint) Temp dst_hint)
{ {
unsigned bytes_size = 0; unsigned bytes_size = 0;
bool mubuf = bld.program->chip_class == GFX6; bool use_mubuf = bld.program->chip_class == GFX6;
bool global = bld.program->chip_class >= GFX9; bool global = bld.program->chip_class >= GFX9;
aco_opcode op; aco_opcode op;
if (bytes_needed == 1) { if (bytes_needed == 1) {
bytes_size = 1; bytes_size = 1;
op = mubuf ? aco_opcode::buffer_load_ubyte : global ? aco_opcode::global_load_ubyte : aco_opcode::flat_load_ubyte; op = use_mubuf ? aco_opcode::buffer_load_ubyte : global ? aco_opcode::global_load_ubyte : aco_opcode::flat_load_ubyte;
} else if (bytes_needed == 2) { } else if (bytes_needed == 2) {
bytes_size = 2; bytes_size = 2;
op = mubuf ? aco_opcode::buffer_load_ushort : global ? aco_opcode::global_load_ushort : aco_opcode::flat_load_ushort; op = use_mubuf ? aco_opcode::buffer_load_ushort : global ? aco_opcode::global_load_ushort : aco_opcode::flat_load_ushort;
} else if (bytes_needed <= 4) { } else if (bytes_needed <= 4) {
bytes_size = 4; bytes_size = 4;
op = mubuf ? aco_opcode::buffer_load_dword : global ? aco_opcode::global_load_dword : aco_opcode::flat_load_dword; op = use_mubuf ? aco_opcode::buffer_load_dword : global ? aco_opcode::global_load_dword : aco_opcode::flat_load_dword;
} else if (bytes_needed <= 8) { } else if (bytes_needed <= 8) {
bytes_size = 8; bytes_size = 8;
op = mubuf ? aco_opcode::buffer_load_dwordx2 : global ? aco_opcode::global_load_dwordx2 : aco_opcode::flat_load_dwordx2; op = use_mubuf ? aco_opcode::buffer_load_dwordx2 : global ? aco_opcode::global_load_dwordx2 : aco_opcode::flat_load_dwordx2;
} else if (bytes_needed <= 12 && !mubuf) { } else if (bytes_needed <= 12 && !use_mubuf) {
bytes_size = 12; bytes_size = 12;
op = global ? aco_opcode::global_load_dwordx3 : aco_opcode::flat_load_dwordx3; op = global ? aco_opcode::global_load_dwordx3 : aco_opcode::flat_load_dwordx3;
} else { } else {
bytes_size = 16; bytes_size = 16;
op = mubuf ? aco_opcode::buffer_load_dwordx4 : global ? aco_opcode::global_load_dwordx4 : aco_opcode::flat_load_dwordx4; op = use_mubuf ? aco_opcode::buffer_load_dwordx4 : global ? aco_opcode::global_load_dwordx4 : aco_opcode::flat_load_dwordx4;
} }
RegClass rc = RegClass::get(RegType::vgpr, align(bytes_size, 4)); RegClass rc = RegClass::get(RegType::vgpr, align(bytes_size, 4));
Temp val = dst_hint.id() && rc == dst_hint.regClass() ? dst_hint : bld.tmp(rc); Temp val = dst_hint.id() && rc == dst_hint.regClass() ? dst_hint : bld.tmp(rc);
if (mubuf) { if (use_mubuf) {
aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)}; aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
mubuf->operands[0] = Operand(get_gfx6_global_rsrc(bld, offset)); mubuf->operands[0] = Operand(get_gfx6_global_rsrc(bld, offset));
mubuf->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1); mubuf->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
@ -3753,13 +3753,13 @@ void store_lds(isel_context *ctx, unsigned elem_size_bytes, Temp data, uint32_t
if (op == aco_opcode::num_opcodes) if (op == aco_opcode::num_opcodes)
continue; continue;
Temp data = write_datas[i]; Temp split_data = write_datas[i];
unsigned second = write_count; unsigned second = write_count;
if (usable_write2 && (op == aco_opcode::ds_write_b32 || op == aco_opcode::ds_write_b64)) { if (usable_write2 && (op == aco_opcode::ds_write_b32 || op == aco_opcode::ds_write_b64)) {
for (second = i + 1; second < write_count; second++) { for (second = i + 1; second < write_count; second++) {
if (opcodes[second] == op && (offsets[second] - offsets[i]) % data.bytes() == 0) { if (opcodes[second] == op && (offsets[second] - offsets[i]) % split_data.bytes() == 0) {
op = data.bytes() == 4 ? aco_opcode::ds_write2_b32 : aco_opcode::ds_write2_b64; op = split_data.bytes() == 4 ? aco_opcode::ds_write2_b32 : aco_opcode::ds_write2_b64;
opcodes[second] = aco_opcode::num_opcodes; opcodes[second] = aco_opcode::num_opcodes;
break; break;
} }
@ -3767,10 +3767,10 @@ void store_lds(isel_context *ctx, unsigned elem_size_bytes, Temp data, uint32_t
} }
bool write2 = op == aco_opcode::ds_write2_b32 || op == aco_opcode::ds_write2_b64; bool write2 = op == aco_opcode::ds_write2_b32 || op == aco_opcode::ds_write2_b64;
unsigned write2_off = (offsets[second] - offsets[i]) / data.bytes(); unsigned write2_off = (offsets[second] - offsets[i]) / split_data.bytes();
unsigned inline_offset = base_offset + offsets[i]; unsigned inline_offset = base_offset + offsets[i];
unsigned max_offset = write2 ? (255 - write2_off) * data.bytes() : 65535; unsigned max_offset = write2 ? (255 - write2_off) * split_data.bytes() : 65535;
Temp address_offset = address; Temp address_offset = address;
if (inline_offset > max_offset) { if (inline_offset > max_offset) {
address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset); address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
@ -3781,10 +3781,10 @@ void store_lds(isel_context *ctx, unsigned elem_size_bytes, Temp data, uint32_t
Instruction *instr; Instruction *instr;
if (write2) { if (write2) {
Temp second_data = write_datas[second]; Temp second_data = write_datas[second];
inline_offset /= data.bytes(); inline_offset /= split_data.bytes();
instr = bld.ds(op, address_offset, data, second_data, m, inline_offset, inline_offset + write2_off); instr = bld.ds(op, address_offset, split_data, second_data, m, inline_offset, inline_offset + write2_off);
} else { } else {
instr = bld.ds(op, address_offset, data, m, inline_offset); instr = bld.ds(op, address_offset, split_data, m, inline_offset);
} }
static_cast<DS_instruction *>(instr)->sync = static_cast<DS_instruction *>(instr)->sync =
memory_sync_info(storage_shared); memory_sync_info(storage_shared);
@ -6863,8 +6863,8 @@ void visit_store_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
for (unsigned i = 0; i < write_count; i++) { for (unsigned i = 0; i < write_count; i++) {
aco_opcode op = get_buffer_store_op(write_datas[i].bytes()); aco_opcode op = get_buffer_store_op(write_datas[i].bytes());
Instruction *instr = bld.mubuf(op, rsrc, offset, ctx->program->scratch_offset, write_datas[i], offsets[i], true, true); Instruction *mubuf = bld.mubuf(op, rsrc, offset, ctx->program->scratch_offset, write_datas[i], offsets[i], true, true);
static_cast<MUBUF_instruction *>(instr)->sync = memory_sync_info(storage_scratch, semantic_private); static_cast<MUBUF_instruction *>(mubuf)->sync = memory_sync_info(storage_scratch, semantic_private);
} }
} }
@ -8647,8 +8647,8 @@ void visit_tex(isel_context *ctx, nir_tex_instr *instr)
switch (instr->src[i].src_type) { switch (instr->src[i].src_type) {
case nir_tex_src_coord: { case nir_tex_src_coord: {
Temp coord = get_ssa_temp(ctx, instr->src[i].src.ssa); Temp coord = get_ssa_temp(ctx, instr->src[i].src.ssa);
for (unsigned i = 0; i < coord.size(); i++) for (unsigned j = 0; j < coord.size(); j++)
coords.emplace_back(emit_extract_vector(ctx, coord, i, v1)); coords.emplace_back(emit_extract_vector(ctx, coord, j, v1));
break; break;
} }
case nir_tex_src_bias: case nir_tex_src_bias:
@ -10671,13 +10671,13 @@ static void emit_stream_output(isel_context *ctx,
if (!num_comps || num_comps > 4) if (!num_comps || num_comps > 4)
return; return;
unsigned start = ffs(output->component_mask) - 1; unsigned first_comp = ffs(output->component_mask) - 1;
Temp out[4]; Temp out[4];
bool all_undef = true; bool all_undef = true;
assert(ctx->stage.hw == HWStage::VS); assert(ctx->stage.hw == HWStage::VS);
for (unsigned i = 0; i < num_comps; i++) { for (unsigned i = 0; i < num_comps; i++) {
out[i] = ctx->outputs.temps[loc * 4 + start + i]; out[i] = ctx->outputs.temps[loc * 4 + first_comp + i];
all_undef = all_undef && !out[i].id(); all_undef = all_undef && !out[i].id();
} }
if (all_undef) if (all_undef)
@ -11075,9 +11075,9 @@ void ngg_emit_sendmsg_gs_alloc_req(isel_context *ctx, Temp vtx_cnt = Temp(), Tem
/* Execute the following code only on the first wave (wave id 0), /* Execute the following code only on the first wave (wave id 0),
* use the SCC def to tell if the wave id is zero or not. * use the SCC def to tell if the wave id is zero or not.
*/ */
Temp cond = wave_id_in_tg.def(1).getTemp(); Temp waveid_as_cond = wave_id_in_tg.def(1).getTemp();
if_context ic; if_context ic;
begin_uniform_if_then(ctx, &ic, cond); begin_uniform_if_then(ctx, &ic, waveid_as_cond);
begin_uniform_if_else(ctx, &ic); begin_uniform_if_else(ctx, &ic);
bld.reset(ctx->block); bld.reset(ctx->block);
@ -11442,8 +11442,6 @@ void ngg_gs_write_shader_query(isel_context *ctx, nir_intrinsic_instr *instr)
begin_uniform_if_then(ctx, &ic_shader_query, shader_query); begin_uniform_if_then(ctx, &ic_shader_query, shader_query);
bld.reset(ctx->block); bld.reset(ctx->block);
Temp gs_vtx_cnt = get_ssa_temp(ctx, instr->src[0].ssa);
Temp gs_prm_cnt = get_ssa_temp(ctx, instr->src[1].ssa);
Temp sg_prm_cnt; Temp sg_prm_cnt;
/* Calculate the "real" number of emitted primitives from the emitted GS vertices and primitives. /* Calculate the "real" number of emitted primitives from the emitted GS vertices and primitives.
@ -11457,9 +11455,10 @@ void ngg_gs_write_shader_query(isel_context *ctx, nir_intrinsic_instr *instr)
Temp thread_cnt = bld.sop1(Builder::s_bcnt1_i32, bld.def(s1), bld.def(s1, scc), Operand(exec, bld.lm)); Temp thread_cnt = bld.sop1(Builder::s_bcnt1_i32, bld.def(s1), bld.def(s1, scc), Operand(exec, bld.lm));
sg_prm_cnt = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), prm_cnt, thread_cnt); sg_prm_cnt = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), prm_cnt, thread_cnt);
} else { } else {
Temp prm_cnt = gs_vtx_cnt; Temp gs_vtx_cnt = get_ssa_temp(ctx, instr->src[0].ssa);
Temp prm_cnt = get_ssa_temp(ctx, instr->src[1].ssa);
if (total_vtx_per_prim > 1) if (total_vtx_per_prim > 1)
prm_cnt = bld.vop3(aco_opcode::v_mad_i32_i24, bld.def(v1), gs_prm_cnt, Operand(-1u * (total_vtx_per_prim - 1)), gs_vtx_cnt); prm_cnt = bld.vop3(aco_opcode::v_mad_i32_i24, bld.def(v1), prm_cnt, Operand(-1u * (total_vtx_per_prim - 1)), gs_vtx_cnt);
else else
prm_cnt = as_vgpr(ctx, prm_cnt); prm_cnt = as_vgpr(ctx, prm_cnt);

8
src/amd/compiler/aco_ir.h
View File

@ -158,8 +158,8 @@ enum sync_scope : uint8_t {
struct memory_sync_info { struct memory_sync_info {
memory_sync_info() : storage(storage_none), semantics(semantic_none), scope(scope_invocation) {} memory_sync_info() : storage(storage_none), semantics(semantic_none), scope(scope_invocation) {}
memory_sync_info(int storage, int semantics=0, sync_scope scope=scope_invocation) memory_sync_info(int storage_, int semantics_=0, sync_scope scope_=scope_invocation)
: storage((storage_class)storage), semantics((memory_semantics)semantics), scope(scope) {} : storage((storage_class)storage_), semantics((memory_semantics)semantics_), scope(scope_) {}
storage_class storage:8; storage_class storage:8;
memory_semantics semantics:8; memory_semantics semantics:8;
@ -281,8 +281,8 @@ struct RegClass {
}; };
RegClass() = default; RegClass() = default;
constexpr RegClass(RC rc) constexpr RegClass(RC rc_)
: rc(rc) {} : rc(rc_) {}
constexpr RegClass(RegType type, unsigned size) constexpr RegClass(RegType type, unsigned size)
: rc((RC) ((type == RegType::vgpr ? 1 << 5 : 0) | size)) {} : rc((RC) ((type == RegType::vgpr ? 1 << 5 : 0) | size)) {}

4
src/amd/compiler/aco_lower_phis.cpp
View File

@ -103,8 +103,8 @@ Operand get_ssa(Program *program, unsigned block_idx, ssa_state *state, bool bef
void insert_before_logical_end(Block *block, aco_ptr<Instruction> instr) void insert_before_logical_end(Block *block, aco_ptr<Instruction> instr)
{ {
auto IsLogicalEnd = [] (const aco_ptr<Instruction>& instr) -> bool { auto IsLogicalEnd = [] (const aco_ptr<Instruction>& inst) -> bool {
return instr->opcode == aco_opcode::p_logical_end; return inst->opcode == aco_opcode::p_logical_end;
}; };
auto it = std::find_if(block->instructions.crbegin(), block->instructions.crend(), IsLogicalEnd); auto it = std::find_if(block->instructions.crbegin(), block->instructions.crend(), IsLogicalEnd);

6
src/amd/compiler/aco_lower_to_cssa.cpp
View File

@ -46,10 +46,8 @@ typedef std::map<uint32_t, std::vector<std::pair<Definition, Operand>>> phi_info
struct cssa_ctx { struct cssa_ctx {
Program* program; Program* program;
live& live_vars; live& live_vars;
phi_info logical_phi_info; phi_info logical_phi_info {};
phi_info linear_phi_info; phi_info linear_phi_info {};
cssa_ctx(Program* program, live& live_vars) : program(program), live_vars(live_vars) {}
}; };
bool collect_phi_info(cssa_ctx& ctx) bool collect_phi_info(cssa_ctx& ctx)

103
src/amd/compiler/aco_lower_to_hw_instr.cpp
View File

@ -1322,12 +1322,10 @@ void handle_operands(std::map<PhysReg, copy_operation>& copy_map, lower_context*
Builder bld(ctx->program, &ctx->instructions); Builder bld(ctx->program, &ctx->instructions);
unsigned num_instructions_before = ctx->instructions.size(); unsigned num_instructions_before = ctx->instructions.size();
aco_ptr<Instruction> mov; aco_ptr<Instruction> mov;
std::map<PhysReg, copy_operation>::iterator it = copy_map.begin();
std::map<PhysReg, copy_operation>::iterator target;
bool writes_scc = false; bool writes_scc = false;
/* count the number of uses for each dst reg */ /* count the number of uses for each dst reg */
while (it != copy_map.end()) { for (auto it = copy_map.begin(); it != copy_map.end();) {
if (it->second.def.physReg() == scc) if (it->second.def.physReg() == scc)
writes_scc = true; writes_scc = true;
@ -1394,8 +1392,7 @@ void handle_operands(std::map<PhysReg, copy_operation>& copy_map, lower_context*
/* first, handle paths in the location transfer graph */ /* first, handle paths in the location transfer graph */
bool preserve_scc = pi->tmp_in_scc && !writes_scc; bool preserve_scc = pi->tmp_in_scc && !writes_scc;
bool skip_partial_copies = true; bool skip_partial_copies = true;
it = copy_map.begin(); for (auto it = copy_map.begin();;) {
while (true) {
if (copy_map.empty()) { if (copy_map.empty()) {
ctx->program->statistics[statistic_copies] += ctx->instructions.size() - num_instructions_before; ctx->program->statistics[statistic_copies] += ctx->instructions.size() - num_instructions_before;
return; return;
@ -1426,13 +1423,13 @@ void handle_operands(std::map<PhysReg, copy_operation>& copy_map, lower_context*
copy_map.erase(it); copy_map.erase(it);
copy_map.erase(other); copy_map.erase(other);
for (std::pair<const PhysReg, copy_operation>& other : copy_map) { for (std::pair<const PhysReg, copy_operation>& other2 : copy_map) {
for (uint16_t i = 0; i < other.second.bytes; i++) { for (uint16_t i = 0; i < other2.second.bytes; i++) {
/* distance might underflow */ /* distance might underflow */
unsigned distance_lo = other.first.reg_b + i - lo.physReg().reg_b; unsigned distance_lo = other2.first.reg_b + i - lo.physReg().reg_b;
unsigned distance_hi = other.first.reg_b + i - hi.physReg().reg_b; unsigned distance_hi = other2.first.reg_b + i - hi.physReg().reg_b;
if (distance_lo < 2 || distance_hi < 2) if (distance_lo < 2 || distance_hi < 2)
other.second.uses[i] -= 1; other2.second.uses[i] -= 1;
} }
} }
it = copy_map.begin(); it = copy_map.begin();
@ -1550,10 +1547,10 @@ void handle_operands(std::map<PhysReg, copy_operation>& copy_map, lower_context*
Operand op; Operand op;
split_copy(offset, &def, &op, original, false, 8); split_copy(offset, &def, &op, original, false, 8);
copy_operation copy = {op, def, def.bytes()}; copy_operation new_copy = {op, def, def.bytes()};
for (unsigned i = 0; i < copy.bytes; i++) for (unsigned i = 0; i < new_copy.bytes; i++)
copy.uses[i] = original.uses[i + offset]; new_copy.uses[i] = original.uses[i + offset];
copy_map[def.physReg()] = copy; copy_map[def.physReg()] = new_copy;
offset += def.bytes(); offset += def.bytes();
} }
@ -1653,9 +1650,8 @@ void handle_operands(std::map<PhysReg, copy_operation>& copy_map, lower_context*
copy_map.erase(it); copy_map.erase(it);
/* change the operand reg of the target's uses and split uses if needed */ /* change the operand reg of the target's uses and split uses if needed */
target = copy_map.begin();
uint32_t bytes_left = u_bit_consecutive(0, swap.bytes); uint32_t bytes_left = u_bit_consecutive(0, swap.bytes);
for (; target != copy_map.end(); ++target) { for (auto target = copy_map.begin(); target != copy_map.end(); ++target) {
if (target->second.op.physReg() == swap.def.physReg() && swap.bytes == target->second.bytes) { if (target->second.op.physReg() == swap.def.physReg() && swap.bytes == target->second.bytes) {
target->second.op.setFixed(swap.op.physReg()); target->second.op.setFixed(swap.op.physReg());
break; break;
@ -1733,38 +1729,43 @@ void emit_set_mode(Builder& bld, float_mode new_mode, bool set_round, bool set_d
} }
} }
void emit_set_mode_from_block(Builder& bld, Program& program, Block* block, bool always_set)
{
float_mode config_mode;
config_mode.val = program.config->float_mode;
bool set_round = always_set && block->fp_mode.round != config_mode.round;
bool set_denorm = always_set && block->fp_mode.denorm != config_mode.denorm;
if (block->kind & block_kind_top_level) {
for (unsigned pred : block->linear_preds) {
if (program.blocks[pred].fp_mode.round != block->fp_mode.round)
set_round = true;
if (program.blocks[pred].fp_mode.denorm != block->fp_mode.denorm)
set_denorm = true;
}
}
/* only allow changing modes at top-level blocks so this doesn't break
* the "jump over empty blocks" optimization */
assert((!set_round && !set_denorm) || (block->kind & block_kind_top_level));
emit_set_mode(bld, block->fp_mode, set_round, set_denorm);
}
void lower_to_hw_instr(Program* program) void lower_to_hw_instr(Program* program)
{ {
Block *discard_block = NULL; Block *discard_block = NULL;
for (size_t i = 0; i < program->blocks.size(); i++) for (size_t block_idx = 0; block_idx < program->blocks.size(); block_idx++)
{ {
Block *block = &program->blocks[i]; Block *block = &program->blocks[block_idx];
lower_context ctx; lower_context ctx;
ctx.program = program; ctx.program = program;
ctx.block = block; ctx.block = block;
Builder bld(program, &ctx.instructions); Builder bld(program, &ctx.instructions);
float_mode config_mode; emit_set_mode_from_block(bld, *program, block, (block_idx == 0));
config_mode.val = program->config->float_mode;
bool set_round = i == 0 && block->fp_mode.round != config_mode.round; for (size_t instr_idx = 0; instr_idx < block->instructions.size(); instr_idx++) {
bool set_denorm = i == 0 && block->fp_mode.denorm != config_mode.denorm; aco_ptr<Instruction>& instr = block->instructions[instr_idx];
if (block->kind & block_kind_top_level) {
for (unsigned pred : block->linear_preds) {
if (program->blocks[pred].fp_mode.round != block->fp_mode.round)
set_round = true;
if (program->blocks[pred].fp_mode.denorm != block->fp_mode.denorm)
set_denorm = true;
}
}
/* only allow changing modes at top-level blocks so this doesn't break
* the "jump over empty blocks" optimization */
assert((!set_round && !set_denorm) || (block->kind & block_kind_top_level));
emit_set_mode(bld, block->fp_mode, set_round, set_denorm);
for (size_t j = 0; j < block->instructions.size(); j++) {
aco_ptr<Instruction>& instr = block->instructions[j];
aco_ptr<Instruction> mov; aco_ptr<Instruction> mov;
if (instr->format == Format::PSEUDO && instr->opcode != aco_opcode::p_unit_test) { if (instr->format == Format::PSEUDO && instr->opcode != aco_opcode::p_unit_test) {
Pseudo_instruction *pi = (Pseudo_instruction*)instr.get(); Pseudo_instruction *pi = (Pseudo_instruction*)instr.get();
@ -1833,9 +1834,9 @@ void lower_to_hw_instr(Program* program)
case aco_opcode::p_wqm: case aco_opcode::p_wqm:
{ {
std::map<PhysReg, copy_operation> copy_operations; std::map<PhysReg, copy_operation> copy_operations;
for (unsigned i = 0; i < instr->operands.size(); i++) { for (unsigned j = 0; j < instr->operands.size(); j++) {
assert(instr->definitions[i].bytes() == instr->operands[i].bytes()); assert(instr->definitions[j].bytes() == instr->operands[j].bytes());
copy_operations[instr->definitions[i].physReg()] = {instr->operands[i], instr->definitions[i], instr->operands[i].bytes()}; copy_operations[instr->definitions[j].physReg()] = {instr->operands[j], instr->definitions[j], instr->operands[j].bytes()};
} }
handle_operands(copy_operations, &ctx, program->chip_class, pi); handle_operands(copy_operations, &ctx, program->chip_class, pi);
break; break;
@ -1843,22 +1844,22 @@ void lower_to_hw_instr(Program* program)
case aco_opcode::p_exit_early_if: case aco_opcode::p_exit_early_if:
{ {
/* don't bother with an early exit near the end of the program */ /* don't bother with an early exit near the end of the program */
if ((block->instructions.size() - 1 - j) <= 4 && if ((block->instructions.size() - 1 - instr_idx) <= 4 &&
block->instructions.back()->opcode == aco_opcode::s_endpgm) { block->instructions.back()->opcode == aco_opcode::s_endpgm) {
unsigned null_exp_dest = (ctx.program->stage.hw == HWStage::FS) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS; unsigned null_exp_dest = (ctx.program->stage.hw == HWStage::FS) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS;
bool ignore_early_exit = true; bool ignore_early_exit = true;
for (unsigned k = j + 1; k < block->instructions.size(); ++k) { for (unsigned k = instr_idx + 1; k < block->instructions.size(); ++k) {
const aco_ptr<Instruction> &instr = block->instructions[k]; const aco_ptr<Instruction> &instr2 = block->instructions[k];
if (instr->opcode == aco_opcode::s_endpgm || if (instr2->opcode == aco_opcode::s_endpgm ||
instr->opcode == aco_opcode::p_logical_end) instr2->opcode == aco_opcode::p_logical_end)
continue; continue;
else if (instr->opcode == aco_opcode::exp && else if (instr2->opcode == aco_opcode::exp &&
static_cast<Export_instruction *>(instr.get())->dest == null_exp_dest) static_cast<Export_instruction *>(instr2.get())->dest == null_exp_dest)
continue; continue;
else if (instr->opcode == aco_opcode::p_parallelcopy && else if (instr2->opcode == aco_opcode::p_parallelcopy &&
instr->definitions[0].isFixed() && instr2->definitions[0].isFixed() &&
instr->definitions[0].physReg() == exec) instr2->definitions[0].physReg() == exec)
continue; continue;
ignore_early_exit = false; ignore_early_exit = false;
@ -1870,7 +1871,7 @@ void lower_to_hw_instr(Program* program)
if (!discard_block) { if (!discard_block) {
discard_block = program->create_and_insert_block(); discard_block = program->create_and_insert_block();
block = &program->blocks[i]; block = &program->blocks[block_idx];
bld.reset(discard_block); bld.reset(discard_block);
bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1), bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),

2
src/amd/compiler/aco_opt_value_numbering.cpp
View File

@ -342,7 +342,7 @@ struct vn_ctx {
*/ */
uint32_t exec_id = 1; uint32_t exec_id = 1;
vn_ctx(Program* program) : program(program) { vn_ctx(Program* program_) : program(program_) {
static_assert(sizeof(Temp) == 4, "Temp must fit in 32bits"); static_assert(sizeof(Temp) == 4, "Temp must fit in 32bits");
unsigned size = 0; unsigned size = 0;
for (Block& block : program->blocks) for (Block& block : program->blocks)

22
src/amd/compiler/aco_optimizer.cpp
View File

@ -378,10 +378,10 @@ struct ssa_info {
return label & label_undefined; return label & label_undefined;
} }
void set_vcc(Temp vcc) void set_vcc(Temp vcc_val)
{ {
add_label(label_vcc); add_label(label_vcc);
temp = vcc; temp = vcc_val;
} }
bool is_vcc() bool is_vcc()
@ -389,10 +389,10 @@ struct ssa_info {
return label & label_vcc; return label & label_vcc;
} }
void set_b2f(Temp val) void set_b2f(Temp b2f_val)
{ {
add_label(label_b2f); add_label(label_b2f);
temp = val; temp = b2f_val;
} }
bool is_b2f() bool is_b2f()
@ -496,10 +496,10 @@ struct ssa_info {
return label & label_vcc_hint; return label & label_vcc_hint;
} }
void set_b2i(Temp val) void set_b2i(Temp b2i_val)
{ {
add_label(label_b2i); add_label(label_b2i);
temp = val; temp = b2i_val;
} }
bool is_b2i() bool is_b2i()
@ -1128,7 +1128,7 @@ void label_instruction(opt_ctx &ctx, Block& block, aco_ptr<Instruction>& instr)
} }
Instruction* vec = ctx.info[op.tempId()].instr; Instruction* vec = ctx.info[op.tempId()].instr;
bool is_subdword = std::any_of(vec->operands.begin(), vec->operands.end(), bool is_subdword = std::any_of(vec->operands.begin(), vec->operands.end(),
[&] (const Operand& op) { return op.bytes() % 4; } ); [&] (const Operand& op2) { return op2.bytes() % 4; } );
if (accept_subdword || !is_subdword) { if (accept_subdword || !is_subdword) {
for (const Operand& vec_op : vec->operands) { for (const Operand& vec_op : vec->operands) {
@ -3374,10 +3374,10 @@ void optimize(Program* program)
} }
/* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */ /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
for (std::vector<Block>::reverse_iterator it = program->blocks.rbegin(); it != program->blocks.rend(); ++it) { for (auto block_rit = program->blocks.rbegin(); block_rit != program->blocks.rend(); ++block_rit) {
Block* block = &(*it); Block* block = &(*block_rit);
for (std::vector<aco_ptr<Instruction>>::reverse_iterator it = block->instructions.rbegin(); it != block->instructions.rend(); ++it) for (auto instr_rit = block->instructions.rbegin(); instr_rit != block->instructions.rend(); ++instr_rit)
select_instruction(ctx, *it); select_instruction(ctx, *instr_rit);
} }
/* 4. Add literals to instructions */ /* 4. Add literals to instructions */

56
src/amd/compiler/aco_register_allocation.cpp
View File

@ -50,7 +50,7 @@ struct assignment {
RegClass rc; RegClass rc;
uint8_t assigned = 0; uint8_t assigned = 0;
assignment() = default; assignment() = default;
assignment(PhysReg reg, RegClass rc) : reg(reg), rc(rc), assigned(-1) {} assignment(PhysReg reg_, RegClass rc_) : reg(reg_), rc(rc_), assigned(-1) {}
}; };
struct phi_info { struct phi_info {
@ -77,12 +77,12 @@ struct ra_ctx {
unsigned max_used_vgpr = 0; unsigned max_used_vgpr = 0;
std::bitset<64> defs_done; /* see MAX_ARGS in aco_instruction_selection_setup.cpp */ std::bitset<64> defs_done; /* see MAX_ARGS in aco_instruction_selection_setup.cpp */
ra_ctx(Program* program) : program(program), ra_ctx(Program* program_) : program(program_),
assignments(program->peekAllocationId()), assignments(program->peekAllocationId()),
renames(program->blocks.size()), renames(program->blocks.size()),
incomplete_phis(program->blocks.size()), incomplete_phis(program->blocks.size()),
filled(program->blocks.size()), filled(program->blocks.size()),
sealed(program->blocks.size()) sealed(program->blocks.size())
{ {
pseudo_dummy.reset(create_instruction<Instruction>(aco_opcode::p_parallelcopy, Format::PSEUDO, 0, 0)); pseudo_dummy.reset(create_instruction<Instruction>(aco_opcode::p_parallelcopy, Format::PSEUDO, 0, 0));
} }
@ -614,10 +614,10 @@ std::pair<PhysReg, bool> get_reg_simple(ra_ctx& ctx,
if (stride == 1) { if (stride == 1) {
info.rc = RegClass(rc.type(), size); info.rc = RegClass(rc.type(), size);
for (unsigned stride = 8; stride > 1; stride /= 2) { for (unsigned new_stride = 8; new_stride > 1; new_stride /= 2) {
if (size % stride) if (size % new_stride)
continue; continue;
info.stride = stride; info.stride = new_stride;
std::pair<PhysReg, bool> res = get_reg_simple(ctx, reg_file, info); std::pair<PhysReg, bool> res = get_reg_simple(ctx, reg_file, info);
if (res.second) if (res.second)
return res; return res;
@ -1365,12 +1365,12 @@ PhysReg get_reg_create_vector(ra_ctx& ctx,
continue; continue;
/* count operands in wrong positions */ /* count operands in wrong positions */
for (unsigned j = 0, offset = 0; j < instr->operands.size(); offset += instr->operands[j].bytes(), j++) { for (unsigned j = 0, offset2 = 0; j < instr->operands.size(); offset2 += instr->operands[j].bytes(), j++) {
if (j == i || if (j == i ||
!instr->operands[j].isTemp() || !instr->operands[j].isTemp() ||
instr->operands[j].getTemp().type() != rc.type()) instr->operands[j].getTemp().type() != rc.type())
continue; continue;
if (instr->operands[j].physReg().reg_b != reg_lo * 4 + offset) if (instr->operands[j].physReg().reg_b != reg_lo * 4 + offset2)
k += instr->operands[j].bytes(); k += instr->operands[j].bytes();
} }
bool aligned = rc == RegClass::v4 && reg_lo % 4 == 0; bool aligned = rc == RegClass::v4 && reg_lo % 4 == 0;
@ -1704,8 +1704,8 @@ void try_remove_trivial_phi(ra_ctx& ctx, Temp temp)
auto it = ctx.orig_names.find(same.id()); auto it = ctx.orig_names.find(same.id());
unsigned orig_var = it != ctx.orig_names.end() ? it->second.id() : same.id(); unsigned orig_var = it != ctx.orig_names.end() ? it->second.id() : same.id();
for (unsigned i = 0; i < ctx.program->blocks.size(); i++) { for (unsigned i = 0; i < ctx.program->blocks.size(); i++) {
auto it = ctx.renames[i].find(orig_var); auto rename_it = ctx.renames[i].find(orig_var);
if (it != ctx.renames[i].end() && it->second == def.getTemp()) if (rename_it != ctx.renames[i].end() && rename_it->second == def.getTemp())
ctx.renames[i][orig_var] = same; ctx.renames[i][orig_var] = same;
} }
@ -1726,8 +1726,8 @@ void register_allocation(Program *program, std::vector<IDSet>& live_out_per_bloc
std::vector<std::vector<Temp>> phi_ressources; std::vector<std::vector<Temp>> phi_ressources;
std::unordered_map<unsigned, unsigned> temp_to_phi_ressources; std::unordered_map<unsigned, unsigned> temp_to_phi_ressources;
for (std::vector<Block>::reverse_iterator it = program->blocks.rbegin(); it != program->blocks.rend(); it++) { for (auto block_rit = program->blocks.rbegin(); block_rit != program->blocks.rend(); block_rit++) {
Block& block = *it; Block& block = *block_rit;
/* first, compute the death points of all live vars within the block */ /* first, compute the death points of all live vars within the block */
IDSet& live = live_out_per_block[block.index]; IDSet& live = live_out_per_block[block.index];
@ -1827,14 +1827,14 @@ void register_allocation(Program *program, std::vector<IDSet>& live_out_per_bloc
} }
std::vector<aco_ptr<Instruction>> instructions; std::vector<aco_ptr<Instruction>> instructions;
std::vector<aco_ptr<Instruction>>::iterator it; std::vector<aco_ptr<Instruction>>::iterator instr_it;
/* this is a slight adjustment from the paper as we already have phi nodes: /* this is a slight adjustment from the paper as we already have phi nodes:
* We consider them incomplete phis and only handle the definition. */ * We consider them incomplete phis and only handle the definition. */
/* handle fixed phi definitions */ /* handle fixed phi definitions */
for (it = block.instructions.begin(); it != block.instructions.end(); ++it) { for (instr_it = block.instructions.begin(); instr_it != block.instructions.end(); ++instr_it) {
aco_ptr<Instruction>& phi = *it; aco_ptr<Instruction>& phi = *instr_it;
if (!is_phi(phi)) if (!is_phi(phi))
break; break;
Definition& definition = phi->definitions[0]; Definition& definition = phi->definitions[0];
@ -1863,8 +1863,8 @@ void register_allocation(Program *program, std::vector<IDSet>& live_out_per_bloc
} }
/* look up the affinities */ /* look up the affinities */
for (it = block.instructions.begin(); it != block.instructions.end(); ++it) { for (instr_it = block.instructions.begin(); instr_it != block.instructions.end(); ++instr_it) {
aco_ptr<Instruction>& phi = *it; aco_ptr<Instruction>& phi = *instr_it;
if (!is_phi(phi)) if (!is_phi(phi))
break; break;
Definition& definition = phi->definitions[0]; Definition& definition = phi->definitions[0];
@ -1897,8 +1897,8 @@ void register_allocation(Program *program, std::vector<IDSet>& live_out_per_bloc
} }
/* find registers for phis without affinity or where the register was blocked */ /* find registers for phis without affinity or where the register was blocked */
for (it = block.instructions.begin();it != block.instructions.end(); ++it) { for (instr_it = block.instructions.begin();instr_it != block.instructions.end(); ++instr_it) {
aco_ptr<Instruction>& phi = *it; aco_ptr<Instruction>& phi = *instr_it;
if (!is_phi(phi)) if (!is_phi(phi))
break; break;
@ -1935,7 +1935,7 @@ void register_allocation(Program *program, std::vector<IDSet>& live_out_per_bloc
if ((*phi_it)->definitions[0].tempId() == pc.first.tempId()) if ((*phi_it)->definitions[0].tempId() == pc.first.tempId())
prev_phi = phi_it->get(); prev_phi = phi_it->get();
} }
phi_it = it; phi_it = instr_it;
while (!prev_phi && is_phi(*++phi_it)) { while (!prev_phi && is_phi(*++phi_it)) {
if ((*phi_it)->definitions[0].tempId() == pc.first.tempId()) if ((*phi_it)->definitions[0].tempId() == pc.first.tempId())
prev_phi = phi_it->get(); prev_phi = phi_it->get();
@ -1980,7 +1980,7 @@ void register_allocation(Program *program, std::vector<IDSet>& live_out_per_bloc
ctx.affinities[op.tempId()] = definition.tempId(); ctx.affinities[op.tempId()] = definition.tempId();
} }
instructions.emplace_back(std::move(*it)); instructions.emplace_back(std::move(*instr_it));
} }
/* fill in sgpr_live_in */ /* fill in sgpr_live_in */
@ -1989,8 +1989,8 @@ void register_allocation(Program *program, std::vector<IDSet>& live_out_per_bloc
sgpr_live_in[block.index][127] = register_file[scc.reg()]; sgpr_live_in[block.index][127] = register_file[scc.reg()];
/* Handle all other instructions of the block */ /* Handle all other instructions of the block */
for (; it != block.instructions.end(); ++it) { for (; instr_it != block.instructions.end(); ++instr_it) {
aco_ptr<Instruction>& instr = *it; aco_ptr<Instruction>& instr = *instr_it;
/* parallelcopies from p_phi are inserted here which means /* parallelcopies from p_phi are inserted here which means
* live ranges of killed operands end here as well */ * live ranges of killed operands end here as well */
@ -2390,7 +2390,7 @@ void register_allocation(Program *program, std::vector<IDSet>& live_out_per_bloc
update_phi_map(ctx, tmp.get(), instr.get()); update_phi_map(ctx, tmp.get(), instr.get());
} }
instructions.emplace_back(std::move(*it)); instructions.emplace_back(std::move(*instr_it));
} /* end for Instr */ } /* end for Instr */

29
src/amd/compiler/aco_spill.cpp
View File

@ -63,10 +63,10 @@ struct spill_ctx {
std::map<Instruction *, bool> remat_used; std::map<Instruction *, bool> remat_used;
unsigned wave_size; unsigned wave_size;
spill_ctx(const RegisterDemand target_pressure, Program* program, spill_ctx(const RegisterDemand target_pressure_, Program* program_,
std::vector<std::vector<RegisterDemand>> register_demand) std::vector<std::vector<RegisterDemand>> register_demand_)
: target_pressure(target_pressure), program(program), : target_pressure(target_pressure_), program(program_),
register_demand(std::move(register_demand)), renames(program->blocks.size()), register_demand(std::move(register_demand_)), renames(program->blocks.size()),
spills_entry(program->blocks.size()), spills_exit(program->blocks.size()), spills_entry(program->blocks.size()), spills_exit(program->blocks.size()),
processed(program->blocks.size(), false), wave_size(program->wave_size) {} processed(program->blocks.size(), false), wave_size(program->wave_size) {}
@ -733,10 +733,11 @@ void add_coupling_code(spill_ctx& ctx, Block* block, unsigned block_idx)
assert(ctx.register_demand[block_idx].size() == block->instructions.size()); assert(ctx.register_demand[block_idx].size() == block->instructions.size());
std::vector<RegisterDemand> reg_demand; std::vector<RegisterDemand> reg_demand;
unsigned insert_idx = 0; unsigned insert_idx = 0;
unsigned pred_idx = block->linear_preds[0];
RegisterDemand demand_before = get_demand_before(ctx, block_idx, 0); RegisterDemand demand_before = get_demand_before(ctx, block_idx, 0);
for (std::pair<Temp, std::pair<uint32_t, uint32_t>> live : ctx.next_use_distances_start[block_idx]) { for (std::pair<Temp, std::pair<uint32_t, uint32_t>> live : ctx.next_use_distances_start[block_idx]) {
const unsigned pred_idx = block->linear_preds[0];
if (!live.first.is_linear()) if (!live.first.is_linear())
continue; continue;
/* still spilled */ /* still spilled */
@ -1221,11 +1222,9 @@ void spill_block(spill_ctx& ctx, unsigned block_idx)
!ctx.renames[block_idx].empty() || !ctx.renames[block_idx].empty() ||
ctx.remat_used.size(); ctx.remat_used.size();
std::map<Temp, uint32_t>::iterator it = current_spills.begin(); for (auto it = current_spills.begin(); !process && it != current_spills.end(); ++it) {
while (!process && it != current_spills.end()) {
if (ctx.next_use_distances_start[block_idx][it->first].first == block_idx) if (ctx.next_use_distances_start[block_idx][it->first].first == block_idx)
process = true; process = true;
++it;
} }
if (process) if (process)
@ -1284,14 +1283,12 @@ void spill_block(spill_ctx& ctx, unsigned block_idx)
instr_it++; instr_it++;
} }
std::map<Temp, std::pair<uint32_t, uint32_t>>::iterator it = ctx.next_use_distances_start[idx].find(rename.first);
/* variable is not live at beginning of this block */ /* variable is not live at beginning of this block */
if (it == ctx.next_use_distances_start[idx].end()) if (ctx.next_use_distances_start[idx].count(rename.first) == 0)
continue; continue;
/* if the variable is live at the block's exit, add rename */ /* if the variable is live at the block's exit, add rename */
if (ctx.next_use_distances_end[idx].find(rename.first) != ctx.next_use_distances_end[idx].end()) if (ctx.next_use_distances_end[idx].count(rename.first) != 0)
ctx.renames[idx].insert(rename); ctx.renames[idx].insert(rename);
/* rename all uses in this block */ /* rename all uses in this block */
@ -1620,8 +1617,8 @@ void assign_spill_slots(spill_ctx& ctx, unsigned spills_to_vgpr) {
} else { } else {
assert(last_top_level_block_idx < block.index); assert(last_top_level_block_idx < block.index);
/* insert before the branch at last top level block */ /* insert before the branch at last top level block */
std::vector<aco_ptr<Instruction>>& instructions = ctx.program->blocks[last_top_level_block_idx].instructions; std::vector<aco_ptr<Instruction>>& block_instrs = ctx.program->blocks[last_top_level_block_idx].instructions;
instructions.insert(std::next(instructions.begin(), instructions.size() - 1), std::move(create)); block_instrs.insert(std::prev(block_instrs.end()), std::move(create));
} }
} }
@ -1689,8 +1686,8 @@ void assign_spill_slots(spill_ctx& ctx, unsigned spills_to_vgpr) {
} else { } else {
assert(last_top_level_block_idx < block.index); assert(last_top_level_block_idx < block.index);
/* insert before the branch at last top level block */ /* insert before the branch at last top level block */
std::vector<aco_ptr<Instruction>>& instructions = ctx.program->blocks[last_top_level_block_idx].instructions; std::vector<aco_ptr<Instruction>>& block_instrs = ctx.program->blocks[last_top_level_block_idx].instructions;
instructions.insert(std::next(instructions.begin(), instructions.size() - 1), std::move(create)); block_instrs.insert(std::prev(block_instrs.end()), std::move(create));
} }
} }

2
src/amd/compiler/aco_ssa_elimination.cpp
View File

@ -39,7 +39,7 @@ struct ssa_elimination_ctx {
std::vector<bool> empty_blocks; std::vector<bool> empty_blocks;
Program* program; Program* program;
ssa_elimination_ctx(Program* program) : empty_blocks(program->blocks.size(), true), program(program) {} ssa_elimination_ctx(Program* program_) : empty_blocks(program_->blocks.size(), true), program(program_) {}
}; };
void collect_phi_info(ssa_elimination_ctx& ctx) void collect_phi_info(ssa_elimination_ctx& ctx)

4
src/amd/compiler/aco_util.h
View File

@ -59,8 +59,8 @@ public:
* \param[in] data Pointer to the underlying data array * \param[in] data Pointer to the underlying data array
* \param[in] length The size of the span * \param[in] length The size of the span
*/ */
constexpr span(uint16_t offset, const size_type length) constexpr span(uint16_t offset_, const size_type length_)
: offset{ offset } , length{ length } {} : offset{ offset_ } , length{ length_ } {}
/*! \brief Returns an iterator to the begin of the span /*! \brief Returns an iterator to the begin of the span
* \return data * \return data

8
src/amd/compiler/aco_validate.cpp
View File

@ -76,8 +76,8 @@ void _aco_err(Program *program, const char *file, unsigned line,
bool validate_ir(Program* program) bool validate_ir(Program* program)
{ {
bool is_valid = true; bool is_valid = true;
auto check = [&program, &is_valid](bool check, const char * msg, aco::Instruction * instr) -> void { auto check = [&program, &is_valid](bool success, const char * msg, aco::Instruction * instr) -> void {
if (!check) { if (!success) {
char *out; char *out;
size_t outsize; size_t outsize;
struct u_memstream mem; struct u_memstream mem;
@ -95,8 +95,8 @@ bool validate_ir(Program* program)
} }
}; };
auto check_block = [&program, &is_valid](bool check, const char * msg, aco::Block * block) -> void { auto check_block = [&program, &is_valid](bool success, const char * msg, aco::Block * block) -> void {
if (!check) { if (!success) {
aco_err(program, "%s: BB%u", msg, block->index); aco_err(program, "%s: BB%u", msg, block->index);
is_valid = false; is_valid = false;
} }