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i965/icl: Don't set float blend optimization bit in CACHE_MODE_SS 

CACHE_MODE_SS is not listed in gfxspecs table for user mode
non-privileged registers. So, making any changes from Mesa
will do nothing. Kernel is already setting this bit in
CACHE_MODE_SS register which is saved/restored to/from
the HW context image.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
Anuj Phogat 2018-05-31 16:03:44 -07:00
parent c1d8300117
commit 2badf0e85b
1 changed files with 0 additions and 4 deletions
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4
src/mesa/drivers/dri/i965/brw_state_upload.c
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@ -64,10 +64,6 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
brw_upload_invariant_state(brw);
if (devinfo->gen == 10 || devinfo->gen == 11) {
brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS,
REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
/* From gen10 workaround table in h/w specs:
*
* "On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1