intel/rt: Add lowering functions for each ray-tracing stage

These will eventually contain per-stage lowering for various ray-tracing
things.  This is separate from brw_nir_lower_rt_intrinsics because, for
reasons that will become apparent later, brw_nir_lower_rt_intrinsics has
to be run very late in the compile process, right before brw_compile_bs.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>

src/intel/Makefile.sources

@@ -98,6 +98,7 @@ COMPILER_FILES = \
 	compiler/brw_nir_lower_scoped_barriers.c \
 	compiler/brw_nir_opt_peephole_ffma.c \
 	compiler/brw_nir_rt.h \
+	compiler/brw_nir_rt.c \
 	compiler/brw_nir_rt_builder.h \
 	compiler/brw_nir_tcs_workarounds.c \
 	compiler/brw_packed_float.c \

src/intel/compiler/brw_nir_rt.c

@@ -0,0 +1,63 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "brw_nir_rt.h"
+
+void
+brw_nir_lower_raygen(nir_shader *nir)
+{
+   assert(nir->info.stage == MESA_SHADER_RAYGEN);
+}
+
+void
+brw_nir_lower_any_hit(nir_shader *nir, const struct gen_device_info *devinfo)
+{
+   assert(nir->info.stage == MESA_SHADER_ANY_HIT);
+}
+
+void
+brw_nir_lower_closest_hit(nir_shader *nir)
+{
+   assert(nir->info.stage == MESA_SHADER_CLOSEST_HIT);
+}
+
+void
+brw_nir_lower_miss(nir_shader *nir)
+{
+   assert(nir->info.stage == MESA_SHADER_MISS);
+}
+
+void
+brw_nir_lower_callable(nir_shader *nir)
+{
+   assert(nir->info.stage == MESA_SHADER_CALLABLE);
+}
+
+void
+brw_nir_lower_combined_intersection_any_hit(nir_shader *intersection,
+                                            const nir_shader *any_hit,
+                                            const struct gen_device_info *devinfo)
+{
+   assert(intersection->info.stage == MESA_SHADER_INTERSECTION);
+   assert(any_hit == NULL || any_hit->info.stage == MESA_SHADER_ANY_HIT);
+}

src/intel/compiler/brw_nir_rt.h

@@ -31,6 +31,16 @@
 extern "C" {
 #endif
 
+void brw_nir_lower_raygen(nir_shader *nir);
+void brw_nir_lower_any_hit(nir_shader *nir,
+                           const struct gen_device_info *devinfo);
+void brw_nir_lower_closest_hit(nir_shader *nir);
+void brw_nir_lower_miss(nir_shader *nir);
+void brw_nir_lower_callable(nir_shader *nir);
+void brw_nir_lower_combined_intersection_any_hit(nir_shader *intersection,
+                                                 const nir_shader *any_hit,
+                                                 const struct gen_device_info *devinfo);
+
 void brw_nir_lower_rt_intrinsics(nir_shader *shader,
                                  const struct gen_device_info *devinfo);
 

src/intel/compiler/meson.build

@@ -89,6 +89,7 @@ libintel_compiler_files = files(
   'brw_nir_lower_scoped_barriers.c',
   'brw_nir_opt_peephole_ffma.c',
   'brw_nir_rt.h',
+  'brw_nir_rt.c',
   'brw_nir_rt_builder.h',
   'brw_nir_tcs_workarounds.c',
   'brw_nir_clamp_image_1d_2d_array_sizes.c',