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freedreno/a6xx: Add new register fields 

Also use them in drivers and delete some comments that are now
irrelevant.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12340>
This commit is contained in:
Connor Abbott 2021-08-12 14:47:40 +02:00 committed by Marge Bot
parent 19b7bbba73
commit 2b134a8c0c
13 changed files with 362 additions and 279 deletions
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86
src/freedreno/.gitlab-ci/reference/crash.log
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@ -819,7 +819,7 @@ registers:
00000000 0xa01: 00000000
00000000 0xa02: 00000000
00000000 CP_APERTURE_CNTL_CD: 0
00000000 0xc00: 00000000
00000000 VSC_DBG_ECO_CNTL: 0
00000001 VSC_ADDR_MODE_CNTL: ADDR_64B
00000101 VSC_BIN_SIZE: { WIDTH = 32 | HEIGHT = 16 }
00000000 VSC_DRAW_STRM_SIZE_ADDRESS: 0
@ -1070,7 +1070,7 @@ registers:
00000000 0xe32: 00000000
00000000 0xe38: 00000000
00000000 0xe39: 00000000
00000000 GRAS_UNKNOWN_8600: 0
00000000 GRAS_DBG_ECO_CNTL: { 0 }
00000001 GRAS_ADDR_MODE_CNTL: ADDR_64B
00000000 GRAS_PERFCTR_TSE_SEL[0]+0: 00000000
00000000 GRAS_PERFCTR_TSE_SEL[0x1]+0: 00000000
@ -1555,7 +1555,7 @@ registers:
00000000 0xa630: 00000000
00100000 RB_UNKNOWN_8E04: 0x100000
00000001 RB_ADDR_MODE_CNTL: ADDR_64B
00000000 RB_CCU_CNTL: { COLOR_OFFSET = 0 }
00000000 RB_CCU_CNTL: { COLOR_OFFSET = 0 | DEPTH_OFFSET = 0 }
00000004 RB_NC_MODE_CNTL: { LOWER_BIT = 2 | UPPER_BIT = 0 }
00000000 RB_PERFCTR_RB_SEL[0]+0: 00000000
00000000 RB_PERFCTR_RB_SEL[0x1]+0: 00000000
@ -1625,12 +1625,12 @@ registers:
00000000 HLSQ_PERFCTR_HLSQ_SEL[0x5]+0: 00000000
00000000 0xbe20: 00000000
00000000 0xbe21: 00000000
00000000 0xbe22: 00000000
00000000 SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE: 0
00000000 0xbe23: 00000000
00000000 SP_UNKNOWN_AE00: 0
00000001 SP_ADDR_MODE_CNTL: ADDR_64B
deadbeef SP_NC_MODE_CNTL: 0xdeadbeef
deadbeef SP_UNKNOWN_AE03: 0xdeadbeef
deadbeef SP_CHICKEN_BITS: 0xdeadbeef
00000004 SP_FLOAT_CNTL: { 0x4 }
deadbeef 0xae0c: deadbeef
deadbeef SP_PERFCTR_ENABLE: { VS | HS | DS | GS | CS | 0xdeadbec0 }
@ -5390,13 +5390,13 @@ clusters:
00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
00000000 GRAS_SU_POLY_OFFSET_OFFSET_CLAMP: 0.000000
00000000 GRAS_SU_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
00000000 GRAS_UNKNOWN_8099: 0
00000000 GRAS_UNKNOWN_809A: 0
00000000 GRAS_SU_CONSERVATIVE_RAS_CNTL: { SHIFTAMOUNT = 0 }
00000000 GRAS_SU_PATH_RENDERING_CNTL: { 0 }
00000000 GRAS_VS_LAYER_CNTL: { 0 }
00000000 GRAS_GS_LAYER_CNTL: { 0 }
00000000 GRAS_DS_LAYER_CNTL: { 0 }
00000002 GRAS_UNKNOWN_80A0: 0x2
00000101 GRAS_BIN_CONTROL: { BINW = 32 | BINH = 16 }
00000002 GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = 0 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD }
00000101 GRAS_BIN_CONTROL: { BINW = 32 | BINH = 16 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 }
00000000 GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 GRAS_SAMPLE_CONFIG: { 0 }
@ -5470,7 +5470,7 @@ clusters:
00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
00000000 GRAS_SC_WINDOW_SCISSOR_BR: { X = 0 | Y = 0 }
00000000 GRAS_LRZ_CNTL: { 0 }
00000000 GRAS_UNKNOWN_8101: 0
00000000 GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
00000000 GRAS_2D_BLIT_INFO: { COLOR_FORMAT = 0 }
00000000 GRAS_LRZ_BUFFER_BASE: 0
00000000 GRAS_LRZ_BUFFER_BASE_HI: 0
@ -5479,7 +5479,7 @@ clusters:
00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
00000000 GRAS_SAMPLE_CNTL: { 0 }
00000000 GRAS_UNKNOWN_8110: 0
00000000 GRAS_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_RAW }
00000000 GRAS_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_RAW | RASTER_MODE = TYPE_TILED }
00000000 GRAS_2D_SRC_TL_X: 0
00000000 GRAS_2D_SRC_BR_X: 0
00000000 GRAS_2D_SRC_TL_Y: 0
@ -5635,13 +5635,13 @@ clusters:
00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
00000000 GRAS_SU_POLY_OFFSET_OFFSET_CLAMP: 0.000000
00000000 GRAS_SU_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
00000000 GRAS_UNKNOWN_8099: 0
00000000 GRAS_UNKNOWN_809A: 0
00000000 GRAS_SU_CONSERVATIVE_RAS_CNTL: { SHIFTAMOUNT = 0 }
00000000 GRAS_SU_PATH_RENDERING_CNTL: { 0 }
00000000 GRAS_VS_LAYER_CNTL: { 0 }
00000000 GRAS_GS_LAYER_CNTL: { 0 }
00000000 GRAS_DS_LAYER_CNTL: { 0 }
00000002 GRAS_UNKNOWN_80A0: 0x2
00000101 GRAS_BIN_CONTROL: { BINW = 32 | BINH = 16 }
00000002 GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = 0 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD }
00000101 GRAS_BIN_CONTROL: { BINW = 32 | BINH = 16 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 }
00000000 GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 GRAS_SAMPLE_CONFIG: { 0 }
@ -5715,7 +5715,7 @@ clusters:
00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
00000000 GRAS_SC_WINDOW_SCISSOR_BR: { X = 0 | Y = 0 }
00000000 GRAS_LRZ_CNTL: { 0 }
00000000 GRAS_UNKNOWN_8101: 0
00000000 GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
00000000 GRAS_2D_BLIT_INFO: { COLOR_FORMAT = 0 }
00000000 GRAS_LRZ_BUFFER_BASE: 0
00000000 GRAS_LRZ_BUFFER_BASE_HI: 0
@ -5724,7 +5724,7 @@ clusters:
00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
00000000 GRAS_SAMPLE_CNTL: { 0 }
00000000 GRAS_UNKNOWN_8110: 0
00000000 GRAS_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_RAW }
00000000 GRAS_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_RAW | RASTER_MODE = TYPE_TILED }
00000000 GRAS_2D_SRC_TL_X: 0
00000000 GRAS_2D_SRC_BR_X: 0
00000000 GRAS_2D_SRC_TL_Y: 0
@ -5738,15 +5738,15 @@ clusters:
00000000 GRAS_2D_RESOLVE_CNTL_2: { X = 0 | Y = 0 }
- cluster-name: CLUSTER_PS
- context: 0
00000101 RB_BIN_CONTROL: { BINW = 32 | BINH = 16 }
00000010 RB_RENDER_CNTL: { UNK4 | FLAG_MRTS = 0 }
00000101 RB_BIN_CONTROL: { BINW = 32 | BINH = 16 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 }
00000010 RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0 }
00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 RB_SAMPLE_CONFIG: { 0 }
00000000 RB_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
00000000 RB_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
00000000 RB_RENDER_CONTROL0: { COORD_MASK = 0 }
00000000 RB_RENDER_CONTROL1: { 0 }
00000000 RB_RENDER_CONTROL1: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
00000000 RB_FS_OUTPUT_CNTL0: { 0 }
00000000 RB_FS_OUTPUT_CNTL1: { MRT = 0 }
00000000 RB_RENDER_COMPONENTS: { RT0 = 0 | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
@ -5901,7 +5901,7 @@ clusters:
00000000 RB_MRT_FLAG_BUFFER[0x7].ADDR: 0
00000000 RB_MRT_FLAG_BUFFER[0x7].ADDR_HI: 0
00000000 RB_MRT_FLAG_BUFFER[0x7].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
00000000 RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_RAW }
00000000 RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_RAW | RASTER_MODE = TYPE_TILED }
00000000 RB_2D_UNKNOWN_8C01: 0
00000000 0x8c08: 00000000
00000000 0x8c09: 00000000
@ -5936,15 +5936,15 @@ clusters:
00000000 0x8c32: 00000000
00000000 0x8c33: 00000000
- context: 1
00000101 RB_BIN_CONTROL: { BINW = 32 | BINH = 16 }
00000010 RB_RENDER_CNTL: { UNK4 | FLAG_MRTS = 0 }
00000101 RB_BIN_CONTROL: { BINW = 32 | BINH = 16 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 }
00000010 RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0 }
00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 RB_SAMPLE_CONFIG: { 0 }
00000000 RB_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
00000000 RB_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
00000000 RB_RENDER_CONTROL0: { COORD_MASK = 0 }
00000000 RB_RENDER_CONTROL1: { 0 }
00000000 RB_RENDER_CONTROL1: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
00000000 RB_FS_OUTPUT_CNTL0: { 0 }
00000000 RB_FS_OUTPUT_CNTL1: { MRT = 0 }
00000000 RB_RENDER_COMPONENTS: { RT0 = 0 | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
@ -6099,7 +6099,7 @@ clusters:
00000000 RB_MRT_FLAG_BUFFER[0x7].ADDR: 0
00000000 RB_MRT_FLAG_BUFFER[0x7].ADDR_HI: 0
00000000 RB_MRT_FLAG_BUFFER[0x7].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
00000000 RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_RAW }
00000000 RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_RAW | RASTER_MODE = TYPE_TILED }
00000000 RB_2D_UNKNOWN_8C01: 0
00000000 0x8c08: 00000000
00000000 0x8c09: 00000000
@ -6331,7 +6331,7 @@ clusters:
00000000 PC_TESS_CNTL: { SPACING = TESS_EQUAL | OUTPUT = TESS_POINTS }
ffffffff PC_RESTART_INDEX: 4294967295
0000001f PC_MODE_CNTL: 0x1f
00000001 PC_UNKNOWN_9805: 0x1
00000001 PC_POWER_CNTL: 0x1
00000000 PC_PRIMID_PASSTHRU: FALSE
00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST }
00000001 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 }
@ -6348,7 +6348,7 @@ clusters:
000000fc VFD_CONTROL_4: { UNK0 = r63.x }
0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x }
00000000 VFD_CONTROL_6: { 0 }
00000000 VFD_MODE_CNTL: { 0 }
00000000 VFD_MODE_CNTL: { RENDER_MODE = RENDERING_PASS }
00000000 VFD_MULTIVIEW_CNTL: { VIEWS = 0 }
00000000 VFD_ADD_OFFSET: { 0 }
00000000 VFD_INDEX_OFFSET: 0
@ -6577,7 +6577,7 @@ clusters:
00000480 VFD_DEST_CNTL[0x1d].INSTR: { WRITEMASK = 0 | REGID = r18.x }
00000000 VFD_DEST_CNTL[0x1e].INSTR: { WRITEMASK = 0 | REGID = r0.x }
00000400 VFD_DEST_CNTL[0x1f].INSTR: { WRITEMASK = 0 | REGID = r16.x }
00000001 SP_UNKNOWN_A0F8: 0x1
00000001 VFD_POWER_CNTL: 0x1
- context: 1
00000000 VPC_UNKNOWN_9300: 0
00ff0001 VPC_VS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
@ -6591,7 +6591,7 @@ clusters:
00000000 PC_TESS_CNTL: { SPACING = TESS_EQUAL | OUTPUT = TESS_POINTS }
ffffffff PC_RESTART_INDEX: 4294967295
0000001f PC_MODE_CNTL: 0x1f
00000001 PC_UNKNOWN_9805: 0x1
00000001 PC_POWER_CNTL: 0x1
00000000 PC_PRIMID_PASSTHRU: FALSE
00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST }
00000001 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 }
@ -6608,7 +6608,7 @@ clusters:
000000fc VFD_CONTROL_4: { UNK0 = r63.x }
0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x }
00000000 VFD_CONTROL_6: { 0 }
00000000 VFD_MODE_CNTL: { 0 }
00000000 VFD_MODE_CNTL: { RENDER_MODE = RENDERING_PASS }
00000000 VFD_MULTIVIEW_CNTL: { VIEWS = 0 }
00000000 VFD_ADD_OFFSET: { 0 }
00000000 VFD_INDEX_OFFSET: 0
@ -6837,10 +6837,10 @@ clusters:
00000480 VFD_DEST_CNTL[0x1d].INSTR: { WRITEMASK = 0 | REGID = r18.x }
00000000 VFD_DEST_CNTL[0x1e].INSTR: { WRITEMASK = 0 | REGID = r0.x }
00000400 VFD_DEST_CNTL[0x1f].INSTR: { WRITEMASK = 0 | REGID = r16.x }
00000001 SP_UNKNOWN_A0F8: 0x1
00000001 VFD_POWER_CNTL: 0x1
- cluster-name: CLUSTER_PC_VS
- context: 0
000000ff VPC_UNKNOWN_9100: 0xff
000000ff VPC_GS_PARAM: { LINELENGTHLOC = 255 }
00ffff00 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
00ffff00 VPC_GS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
00ffff00 VPC_DS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
@ -6867,7 +6867,7 @@ clusters:
00000000 PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 }
00000000 PC_MULTIVIEW_CNTL: { VIEWS = 0 }
- context: 1
000000ff VPC_UNKNOWN_9100: 0xff
000000ff VPC_GS_PARAM: { LINELENGTHLOC = 255 }
00ffff00 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
00ffff00 VPC_GS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
00ffff00 VPC_DS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
@ -7237,7 +7237,7 @@ clusters:
deadbeef HLSQ_2D_EVENT_CMD: { STATE_ID = 0xbe | EVENT = 0x6f | 0xdead0080 }
- cluster-name: CLUSTER_SP_VS
- context: 0
00000000 SP_MODE_CONTROL: { 0 }
00000000 SP_MODE_CONTROL: { ISAMMODE = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_FS_INSTRLEN: 0
2764a40a SP_BINDLESS_BASE[0].ADDR: 0x2764a40a
@ -7254,7 +7254,7 @@ clusters:
00013c40 SP_IBO_HI: 0x13c40
00000040 SP_IBO_COUNT: 64
- context: 1
00000000 SP_MODE_CONTROL: { 0 }
00000000 SP_MODE_CONTROL: { ISAMMODE = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_FS_INSTRLEN: 0
2764a40a SP_BINDLESS_BASE[0].ADDR: 0x2764a40a
@ -7280,7 +7280,7 @@ clusters:
00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 }
0000004c SP_TP_UNKNOWN_B309: 76
0000004c SP_TP_MODE_CNTL: { ISAMMODE = 0 | UNK3 = 0x13 }
deadbeef 0xb380: deadbeef
deadbeef 0xb381: deadbeef
deadbeef 0xb382: deadbeef
@ -7293,7 +7293,7 @@ clusters:
00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 }
0000004c SP_TP_UNKNOWN_B309: 76
0000004c SP_TP_MODE_CNTL: { ISAMMODE = 0 | UNK3 = 0x13 }
deadbeef 0xb380: deadbeef
deadbeef 0xb381: deadbeef
deadbeef 0xb382: deadbeef
@ -7304,7 +7304,7 @@ clusters:
fcfcfcfc HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x }
fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
fcfcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x }
000000fc HLSQ_CONTROL_5_REG: { UNK0 = r63.x }
000000fc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
00000101 HLSQ_CS_CNTL: { CONSTLEN = 4 | ENABLED }
000003fd HLSQ_CS_NDRANGE_0: { KERNELDIM = 1 | LOCALSIZEX = 255 | LOCALSIZEY = 0 | LOCALSIZEZ = 0 }
00000200 HLSQ_CS_NDRANGE_1: { GLOBALSIZE_X = 512 }
@ -7337,7 +7337,7 @@ clusters:
fcfcfcfc HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x }
fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
fcfcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x }
000000fc HLSQ_CONTROL_5_REG: { UNK0 = r63.x }
000000fc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
00000101 HLSQ_CS_CNTL: { CONSTLEN = 4 | ENABLED }
000003fd HLSQ_CS_NDRANGE_0: { KERNELDIM = 1 | LOCALSIZEX = 255 | LOCALSIZEY = 0 | LOCALSIZEZ = 0 }
00000200 HLSQ_CS_NDRANGE_1: { GLOBALSIZE_X = 512 }
@ -7622,7 +7622,7 @@ clusters:
00000000 HLSQ_BINDLESS_BASE[0x4].ADDR_HI: 0
- cluster-name: CLUSTER_SP_PS
- context: 0
00000000 SP_MODE_CONTROL: { 0 }
00000000 SP_MODE_CONTROL: { ISAMMODE = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_FS_INSTRLEN: 0
cdb94116 SP_BINDLESS_BASE[0].ADDR: 0xcdb94116
@ -7639,7 +7639,7 @@ clusters:
00010202 SP_IBO_HI: 0x10202
00000040 SP_IBO_COUNT: 64
- context: 1
00000000 SP_MODE_CONTROL: { 0 }
00000000 SP_MODE_CONTROL: { ISAMMODE = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_FS_INSTRLEN: 0
cdb94116 SP_BINDLESS_BASE[0].ADDR: 0xcdb94116
@ -7665,7 +7665,7 @@ clusters:
00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 }
0000004c SP_TP_UNKNOWN_B309: 76
0000004c SP_TP_MODE_CNTL: { ISAMMODE = 0 | UNK3 = 0x13 }
deadbeef 0xb380: deadbeef
deadbeef 0xb381: deadbeef
deadbeef 0xb382: deadbeef
@ -7678,7 +7678,7 @@ clusters:
00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 }
0000004c SP_TP_UNKNOWN_B309: 76
0000004c SP_TP_MODE_CNTL: { ISAMMODE = 0 | UNK3 = 0x13 }
deadbeef 0xb380: deadbeef
deadbeef 0xb381: deadbeef
deadbeef 0xb382: deadbeef

88
src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
View File

@ -13,7 +13,7 @@ t4 write HLSQ_INVALIDATE_CMD (bb08)
t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
0000000001058010: 0000: 70268000
t4 write RB_CCU_CNTL (8e07)
RB_CCU_CNTL: { COLOR_OFFSET = 0x20000 }
RB_CCU_CNTL: { COLOR_OFFSET = 0x20000 | DEPTH_OFFSET = 0 }
0000000001058014: 0000: 408e0701 10000000
t4 write RB_UNKNOWN_8E04 (8e04)
RB_UNKNOWN_8E04: 0x100000
@ -42,14 +42,14 @@ t4 write HLSQ_UNKNOWN_BE01 (be01)
t4 write VPC_UNKNOWN_9600 (9600)
VPC_UNKNOWN_9600: 0
000000000105805c: 0000: 48960001 00000000
t4 write GRAS_UNKNOWN_8600 (8600)
GRAS_UNKNOWN_8600: 0x880
t4 write GRAS_DBG_ECO_CNTL (8600)
GRAS_DBG_ECO_CNTL: { UNK7 | LRZCACHELOCKDIS }
0000000001058064: 0000: 40860001 00000880
t4 write HLSQ_UNKNOWN_BE04 (be04)
HLSQ_UNKNOWN_BE04: 0
000000000105806c: 0000: 40be0401 00000000
t4 write SP_UNKNOWN_AE03 (ae03)
SP_UNKNOWN_AE03: 0x410
t4 write SP_CHICKEN_BITS (ae03)
SP_CHICKEN_BITS: 0x410
0000000001058074: 0000: 40ae0301 00000410
t4 write SP_IBO_COUNT (ab20)
SP_IBO_COUNT: 0
@ -76,7 +76,7 @@ t4 write SP_UNKNOWN_A9A8 (a9a8)
SP_UNKNOWN_A9A8: 0
00000000010580b4: 0000: 40a9a801 00000000
t4 write SP_MODE_CONTROL (ab00)
SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | UNK2 }
SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
00000000010580bc: 0000: 40ab0001 00000005
t4 write VFD_ADD_OFFSET (a009)
VFD_ADD_OFFSET: { VERTEX }
@ -97,7 +97,7 @@ t4 write RB_RENDER_CONTROL0 (8809)
RB_RENDER_CONTROL0: { IJ_PERSP_PIXEL | COORD_MASK = 0 | UNK10 }
00000000010580ec: 0000: 48880901 00000401
t4 write RB_RENDER_CONTROL1 (880a)
RB_RENDER_CONTROL1: { 0 }
RB_RENDER_CONTROL1: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
00000000010580f4: 0000: 48880a01 00000000
t4 write RB_FS_OUTPUT_CNTL0 (880b)
RB_FS_OUTPUT_CNTL0: { 0 }
@ -153,11 +153,11 @@ t4 write SP_VS_OBJ_FIRST_EXEC_OFFSET (a81b)
t4 write SP_UNKNOWN_B183 (b183)
SP_UNKNOWN_B183: 0
0000000001058184: 0000: 40b18301 00000000
t4 write GRAS_UNKNOWN_8099 (8099)
GRAS_UNKNOWN_8099: 0
t4 write GRAS_SU_CONSERVATIVE_RAS_CNTL (8099)
GRAS_SU_CONSERVATIVE_RAS_CNTL: { SHIFTAMOUNT = 0 }
000000000105818c: 0000: 40809901 00000000
t4 write GRAS_UNKNOWN_80A0 (80a0)
GRAS_UNKNOWN_80A0: 0x2
t4 write GRAS_SC_CNTL (80a0)
GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = 0 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD }
0000000001058194: 0000: 4080a001 00000002
t4 write GRAS_UNKNOWN_80AF (80af)
GRAS_UNKNOWN_80AF: FALSE
@ -174,14 +174,14 @@ t4 write VPC_UNKNOWN_9602 (9602)
t4 write PC_UNKNOWN_9E72 (9e72)
PC_UNKNOWN_9E72: 0
00000000010581bc: 0000: 409e7201 00000000
t4 write SP_TP_UNKNOWN_B309 (b309)
SP_TP_UNKNOWN_B309: 162
t4 write SP_TP_MODE_CNTL (b309)
SP_TP_MODE_CNTL: { ISAMMODE = ISAMMODE_GL | UNK3 = 0x28 }
00000000010581c4: 0000: 40b30901 000000a2
t4 write HLSQ_CONTROL_5_REG (b986)
HLSQ_CONTROL_5_REG: { UNK0 = r63.x }
HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
00000000010581cc: 0000: 48b98601 000000fc
t4 write VFD_MODE_CNTL (a007)
VFD_MODE_CNTL: { 0 }
VFD_MODE_CNTL: { RENDER_MODE = RENDERING_PASS }
00000000010581d4: 0000: 40a00701 00000000
t4 write VFD_MULTIVIEW_CNTL (a008)
VFD_MULTIVIEW_CNTL: { VIEWS = 0 }
@ -243,10 +243,10 @@ t4 write RB_2D_UNKNOWN_8C01 (8c01)
RB_2D_UNKNOWN_8C01: 0
0000000001058278: 0000: 488c0101 00000000
t4 write RB_2D_BLIT_CNTL (8c00)
RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 }
RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 | RASTER_MODE = TYPE_TILED }
0000000001058280: 0000: 408c0001 10f03080
t4 write GRAS_2D_BLIT_CNTL (8400)
GRAS_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 }
GRAS_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 | RASTER_MODE = TYPE_TILED }
0000000001058288: 0000: 48840001 10f03080
t4 write SP_2D_DST_FORMAT (acc0)
SP_2D_DST_FORMAT: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf }
@ -285,17 +285,17 @@ t7 opcode: CP_BLIT (2c) (2 dwords)
+ 00000000 VSC_DRAW_STRM_ADDRESS_HI: 0
!+ 03200000 UCHE_UNKNOWN_0E12: 0x3200000
!+ 00000004 UCHE_CLIENT_PF: { PERFSEL = 0x4 }
+ 00000000 GRAS_UNKNOWN_8099: 0
!+ 00000002 GRAS_UNKNOWN_80A0: 0x2
+ 00000000 GRAS_SU_CONSERVATIVE_RAS_CNTL: { SHIFTAMOUNT = 0 }
!+ 00000002 GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = 0 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD }
+ 00000000 GRAS_UNKNOWN_80AF: FALSE
+ 00000000 GRAS_LRZ_CNTL: { 0 }
+ 00000000 GRAS_UNKNOWN_8110: 0
!+ 10f03080 GRAS_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 }
!+ 10f03080 GRAS_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 | RASTER_MODE = TYPE_TILED }
+ 00000000 GRAS_2D_DST_TL: { X = 0 | Y = 0 }
!+ 00ff00ff GRAS_2D_DST_BR: { X = 255 | Y = 255 }
!+ 00000880 GRAS_UNKNOWN_8600: 0x880
!+ 00000880 GRAS_DBG_ECO_CNTL: { UNK7 | LRZCACHELOCKDIS }
!+ 00000401 RB_RENDER_CONTROL0: { IJ_PERSP_PIXEL | COORD_MASK = 0 | UNK10 }
+ 00000000 RB_RENDER_CONTROL1: { 0 }
+ 00000000 RB_RENDER_CONTROL1: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
+ 00000000 RB_FS_OUTPUT_CNTL0: { 0 }
+ 00000000 RB_SRGB_CNTL: { 0 }
!+ 00000010 RB_UNKNOWN_8811: 0x1
@ -308,7 +308,7 @@ t7 opcode: CP_BLIT (2c) (2 dwords)
+ 00000000 RB_UNKNOWN_881E: 0
+ 00000000 RB_LRZ_CNTL: { 0 }
+ 00000000 RB_UNKNOWN_88F0: 0
!+ 10f03080 RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 }
!+ 10f03080 RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 | RASTER_MODE = TYPE_TILED }
+ 00000000 RB_2D_UNKNOWN_8C01: 0
!+ 00001330 RB_2D_DST_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX | FLAGS | SAMPLES = MSAA_ONE }
!+ 01013000 RB_2D_DST: 0x1013000
@ -323,7 +323,7 @@ t7 opcode: CP_BLIT (2c) (2 dwords)
!+ 000000ff RB_2D_SRC_SOLID_C3: 0xff
+ 00000000 RB_UNKNOWN_8E01: 0
!+ 00100000 RB_UNKNOWN_8E04: 0x100000
!+ 10000000 RB_CCU_CNTL: { COLOR_OFFSET = 0x20000 }
!+ 10000000 RB_CCU_CNTL: { COLOR_OFFSET = 0x20000 | DEPTH_OFFSET = 0 }
+ 00000000 VPC_UNKNOWN_9107: { 0 }
+ 00000000 VPC_UNKNOWN_9210: 0
+ 00000000 VPC_UNKNOWN_9211: 0
@ -337,7 +337,7 @@ t7 opcode: CP_BLIT (2c) (2 dwords)
+ 00000000 PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 }
+ 00000000 PC_MULTIVIEW_CNTL: { VIEWS = 0 }
+ 00000000 PC_UNKNOWN_9E72: 0
+ 00000000 VFD_MODE_CNTL: { 0 }
+ 00000000 VFD_MODE_CNTL: { RENDER_MODE = RENDERING_PASS }
+ 00000000 VFD_MULTIVIEW_CNTL: { VIEWS = 0 }
!+ 00000001 VFD_ADD_OFFSET: { VERTEX }
+ 00000000 SP_VS_OBJ_FIRST_EXEC_OFFSET: 0
@ -345,11 +345,11 @@ t7 opcode: CP_BLIT (2c) (2 dwords)
+ 00000000 SP_GS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
+ 00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0
+ 00000000 SP_UNKNOWN_A9A8: 0
!+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | UNK2 }
!+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
+ 00000000 SP_IBO_COUNT: 0
!+ 0000f180 SP_2D_DST_FORMAT: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf }
+ 00000000 SP_UNKNOWN_AE00: 0
!+ 00000410 SP_UNKNOWN_AE03: 0x410
!+ 00000410 SP_CHICKEN_BITS: 0x410
!+ 00000008 SP_FLOAT_CNTL: { F16_NO_INF }
!+ 0000003f SP_PERFCTR_ENABLE: { VS | HS | DS | GS | FS | CS }
!+ 01011000 SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
@ -358,10 +358,10 @@ t7 opcode: CP_BLIT (2c) (2 dwords)
+ 00000000 SP_UNKNOWN_B183: 0
!+ 01011000 SP_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
+ 00000000 SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0
!+ 000000a2 SP_TP_UNKNOWN_B309: 162
!+ 000000a2 SP_TP_MODE_CNTL: { ISAMMODE = ISAMMODE_GL | UNK3 = 0x28 }
!+ 00100000 TPL1_UNKNOWN_B600: 0x100000
!+ 00000044 TPL1_UNKNOWN_B605: 68
!+ 000000fc HLSQ_CONTROL_5_REG: { UNK0 = r63.x }
!+ 000000fc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
!+ 000fffff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
+ 00000000 HLSQ_SHARED_CONSTS: { 0 }
!+ 00000080 HLSQ_UNKNOWN_BE00: 0x80
@ -399,16 +399,16 @@ t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
000000000105832c: 0000: 70268000
t4 write RB_CCU_CNTL (8e07)
RB_CCU_CNTL: { COLOR_OFFSET = 0xf8000 | GMEM }
RB_CCU_CNTL: { COLOR_OFFSET = 0xf8000 | DEPTH_OFFSET = 0 | GMEM }
0000000001058330: 0000: 408e0701 7c400000
t4 write VPC_SO_DISABLE (9306)
VPC_SO_DISABLE: { 0 }
0000000001058338: 0000: 48930601 00000000
t4 write GRAS_BIN_CONTROL (80a1)
GRAS_BIN_CONTROL: { BINW = 256 | BINH = 256 | UNK22 = 0x18 }
GRAS_BIN_CONTROL: { BINW = 256 | BINH = 256 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
0000000001058340: 0000: 4880a101 06001008
t4 write RB_BIN_CONTROL (8800)
RB_BIN_CONTROL: { BINW = 256 | BINH = 256 | UNK22 = 0x18 }
RB_BIN_CONTROL: { BINW = 256 | BINH = 256 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
0000000001058348: 0000: 48880001 06001008
t4 write RB_BIN_CONTROL2 (88d3)
RB_BIN_CONTROL2: { BINW = 256 | BINH = 256 }
@ -483,12 +483,12 @@ t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
mode: RM6_GMEM
skip_ib2: g=0, l=0
draw[1] register values
!+ 06001008 GRAS_BIN_CONTROL: { BINW = 256 | BINH = 256 | UNK22 = 0x18 }
!+ 06001008 GRAS_BIN_CONTROL: { BINW = 256 | BINH = 256 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
+ 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+ 00ff00ff GRAS_SC_WINDOW_SCISSOR_BR: { X = 255 | Y = 255 }
+ 00000000 GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 }
!+ 00ff00ff GRAS_2D_RESOLVE_CNTL_2: { X = 255 | Y = 255 }
!+ 06001008 RB_BIN_CONTROL: { BINW = 256 | BINH = 256 | UNK22 = 0x18 }
!+ 06001008 RB_BIN_CONTROL: { BINW = 256 | BINH = 256 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
+ 00000000 RB_WINDOW_OFFSET: { X = 0 | Y = 0 }
+ 00000000 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
!+ 00ff00ff RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
@ -504,7 +504,7 @@ t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
+ 00000000 RB_BLIT_FLAG_DST_HI: 0
!+ 00004001 RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
!+ 00000003 RB_BLIT_INFO: { UNK0 | GMEM | CLEAR_MASK = 0 }
!+ 7c400000 RB_CCU_CNTL: { COLOR_OFFSET = 0xf8000 | GMEM }
!+ 7c400000 RB_CCU_CNTL: { COLOR_OFFSET = 0xf8000 | DEPTH_OFFSET = 0 | GMEM }
!+ 00000000 VPC_SO_DISABLE: { 0 }
+ 00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 }
+ 00000000 SP_WINDOW_OFFSET: { X = 0 | Y = 0 }
@ -584,7 +584,7 @@ t7 opcode: CP_COND_REG_EXEC (47) (3 dwords)
000000000115e130: 0000: 70c70002 3c000000 00000004
t7 opcode: CP_REG_WRITE (6d) (4 dwords)
{ TRACKER = TRACK_RENDER_CNTL }
RB_RENDER_CNTL: { UNK4 | FLAG_MRTS = 0x1 }
RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0x1 }
000000000115e13c: 0000: 706d8003 00000002 00008801 00010010
t7 opcode: CP_SET_DRAW_STATE (43) (7 dwords)
{ COUNT = 0 | DISABLE | GMEM | GROUP_ID = 17 }
@ -1004,7 +1004,7 @@ t4 write HLSQ_CONTROL_1_REG (b982)
HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x }
HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x }
HLSQ_CONTROL_5_REG: { UNK0 = r63.x }
HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
000000000105434c: 0000: 40b98285 00000007 fcfcfcfc fcfcfc00 fcfcfcfc 000000fc
t4 write HLSQ_FS_CNTL_0 (b980)
HLSQ_FS_CNTL_0: { THREADSIZE = THREAD128 | VARYINGS }
@ -1014,13 +1014,13 @@ t4 write GRAS_CNTL (8005)
000000000105436c: 0000: 40800501 00000001
t4 write RB_RENDER_CONTROL0 (8809)
RB_RENDER_CONTROL0: { IJ_PERSP_PIXEL | COORD_MASK = 0 | UNK10 }
RB_RENDER_CONTROL1: { 0 }
RB_RENDER_CONTROL1: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
0000000001054374: 0000: 48880902 00000401 00000000
t4 write RB_SAMPLE_CNTL (8810)
RB_SAMPLE_CNTL: { 0 }
0000000001054380: 0000: 40881001 00000000
t4 write GRAS_UNKNOWN_8101 (8101)
GRAS_UNKNOWN_8101: 0
t4 write GRAS_LRZ_PS_INPUT_CNTL (8101)
GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
0000000001054388: 0000: 40810101 00000000
t4 write GRAS_SAMPLE_CNTL (8109)
GRAS_SAMPLE_CNTL: { 0 }
@ -1340,19 +1340,19 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
!+ 00ff00ff GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 255 | Y = 255 }
+ 00000000 GRAS_SC_VIEWPORT_SCISSOR[0].TL: { X = 0 | Y = 0 }
!+ 00ff00ff GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 255 | Y = 255 }
+ 00000000 GRAS_UNKNOWN_8101: 0
+ 00000000 GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
+ 00000000 GRAS_LRZ_BUFFER_BASE: 0
+ 00000000 GRAS_LRZ_BUFFER_BASE_HI: 0
+ 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
+ 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0
+ 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
+ 00000000 GRAS_SAMPLE_CNTL: { 0 }
!+ 00010010 RB_RENDER_CNTL: { UNK4 | FLAG_MRTS = 0x1 }
!+ 00010010 RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0x1 }
+ 00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
!+ 00000004 RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
+ 00000000 RB_SAMPLE_CONFIG: { 0 }
+ 00000401 RB_RENDER_CONTROL0: { IJ_PERSP_PIXEL | COORD_MASK = 0 | UNK10 }
+ 00000000 RB_RENDER_CONTROL1: { 0 }
+ 00000000 RB_RENDER_CONTROL1: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
+ 00000000 RB_FS_OUTPUT_CNTL0: { 0 }
!+ 00000001 RB_FS_OUTPUT_CNTL1: { MRT = 1 }
!+ 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
@ -1532,7 +1532,7 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
!+ fcfcfcfc HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x }
!+ fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
!+ fcfcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x }
+ 000000fc HLSQ_CONTROL_5_REG: { UNK0 = r63.x }
+ 000000fc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
+ 00000000 HLSQ_CS_CNTL: { CONSTLEN = 0 }
!+ 0000009f HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
!+ 00000100 HLSQ_FS_CNTL: { CONSTLEN = 0 | ENABLED }

156
src/freedreno/.gitlab-ci/reference/fd-clouds.log
View File

@ -39,14 +39,14 @@ t4 write HLSQ_UNKNOWN_BE01 (be01)
t4 write VPC_UNKNOWN_9600 (9600)
VPC_UNKNOWN_9600: 0
0000000001d91054: 0000: 48960001 00000000
t4 write GRAS_UNKNOWN_8600 (8600)
GRAS_UNKNOWN_8600: 0x880
t4 write GRAS_DBG_ECO_CNTL (8600)
GRAS_DBG_ECO_CNTL: { UNK7 | LRZCACHELOCKDIS }
0000000001d9105c: 0000: 40860001 00000880
t4 write HLSQ_UNKNOWN_BE04 (be04)
HLSQ_UNKNOWN_BE04: 0x80000
0000000001d91064: 0000: 40be0401 00080000
t4 write SP_UNKNOWN_AE03 (ae03)
SP_UNKNOWN_AE03: 0x1430
t4 write SP_CHICKEN_BITS (ae03)
SP_CHICKEN_BITS: 0x1430
0000000001d9106c: 0000: 40ae0301 00001430
t4 write SP_IBO_COUNT (ab20)
SP_IBO_COUNT: 0
@ -67,7 +67,7 @@ t4 write RB_UNKNOWN_8E01 (8e01)
RB_UNKNOWN_8E01: 0x1
0000000001d9109c: 0000: 408e0101 00000001
t4 write SP_MODE_CONTROL (ab00)
SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | UNK2 }
SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
0000000001d910a4: 0000: 40ab0001 00000005
t4 write VFD_ADD_OFFSET (a009)
VFD_ADD_OFFSET: { VERTEX }
@ -81,8 +81,8 @@ t4 write PC_MODE_CNTL (9804)
t4 write RB_SRGB_CNTL (880f)
RB_SRGB_CNTL: { 0 }
0000000001d910c4: 0000: 48880f01 00000000
t4 write GRAS_UNKNOWN_8101 (8101)
GRAS_UNKNOWN_8101: 0
t4 write GRAS_LRZ_PS_INPUT_CNTL (8101)
GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
0000000001d910cc: 0000: 40810101 00000000
t4 write GRAS_SAMPLE_CNTL (8109)
GRAS_SAMPLE_CNTL: { 0 }
@ -141,14 +141,14 @@ t4 write SP_VS_OBJ_FIRST_EXEC_OFFSET (a81b)
t4 write SP_UNKNOWN_B183 (b183)
SP_UNKNOWN_B183: 0
0000000001d91164: 0000: 40b18301 00000000
t4 write GRAS_UNKNOWN_8099 (8099)
GRAS_UNKNOWN_8099: 0
t4 write GRAS_SU_CONSERVATIVE_RAS_CNTL (8099)
GRAS_SU_CONSERVATIVE_RAS_CNTL: { SHIFTAMOUNT = 0 }
0000000001d9116c: 0000: 40809901 00000000
t4 write GRAS_VS_LAYER_CNTL (809b)
GRAS_VS_LAYER_CNTL: { 0 }
0000000001d91174: 0000: 48809b01 00000000
t4 write GRAS_UNKNOWN_80A0 (80a0)
GRAS_UNKNOWN_80A0: 0x2
t4 write GRAS_SC_CNTL (80a0)
GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = 0 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD }
0000000001d9117c: 0000: 4080a001 00000002
t4 write GRAS_UNKNOWN_80AF (80af)
GRAS_UNKNOWN_80AF: FALSE
@ -174,8 +174,8 @@ t4 write VPC_POLYGON_MODE (9108)
t4 write SP_TP_SAMPLE_CONFIG (b304)
SP_TP_SAMPLE_CONFIG: { 0 }
0000000001d911bc: 0000: 48b30401 00000000
t4 write SP_TP_UNKNOWN_B309 (b309)
SP_TP_UNKNOWN_B309: 162
t4 write SP_TP_MODE_CNTL (b309)
SP_TP_MODE_CNTL: { ISAMMODE = ISAMMODE_GL | UNK3 = 0x28 }
0000000001d911c4: 0000: 40b30901 000000a2
t4 write RB_SAMPLE_CONFIG (8804)
RB_SAMPLE_CONFIG: { 0 }
@ -202,7 +202,7 @@ t4 write RB_Z_BOUNDS_MAX (8879)
RB_Z_BOUNDS_MAX: 0.000000
0000000001d91204: 0000: 40887901 00000000
t4 write HLSQ_CONTROL_5_REG (b986)
HLSQ_CONTROL_5_REG: { UNK0 = r63.x }
HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
0000000001d9120c: 0000: 48b98601 000000fc
t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
0000000001d91214: 0000: 70268000
@ -211,7 +211,7 @@ t4 write CP_SCRATCH[0x7].REG (088a)
:0,0,0,4
0000000001d91218: 0000: 48088a01 00000004
t4 write VFD_MODE_CNTL (a007)
VFD_MODE_CNTL: { 0 }
VFD_MODE_CNTL: { RENDER_MODE = RENDERING_PASS }
0000000001d91220: 0000: 40a00701 00000000
t4 write VFD_MULTIVIEW_CNTL (a008)
VFD_MULTIVIEW_CNTL: { VIEWS = 0 }
@ -246,7 +246,7 @@ t7 opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
0000000001d91278: 0000: 70268000
t4 write RB_CCU_CNTL (8e07)
RB_CCU_CNTL: { COLOR_OFFSET = 0xf8000 | GMEM | UNK2 }
RB_CCU_CNTL: { COLOR_OFFSET = 0xf8000 | DEPTH_OFFSET = 0 | GMEM | UNK2 }
0000000001d9127c: 0000: 408e0701 7c400004
t4 write RB_DEPTH_BUFFER_INFO (8872)
RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
@ -319,17 +319,17 @@ t4 write VPC_SO_DISABLE (9306)
VPC_SO_DISABLE: { 0 }
0000000001d91350: 0000: 48930601 00000000
t4 write GRAS_BIN_CONTROL (80a1)
GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | BINNING_PASS | UNK22 = 0x18 }
GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = BINNING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
0000000001d91358: 0000: 4880a101 06041e11
t4 write RB_BIN_CONTROL (8800)
RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | BINNING_PASS | UNK22 = 0x18 }
RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = BINNING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
0000000001d91360: 0000: 48880001 06041e11
t4 write RB_BIN_CONTROL2 (88d3)
RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 }
0000000001d91368: 0000: 4088d301 00001e11
t7 opcode: CP_REG_WRITE (6d) (4 dwords)
{ TRACKER = TRACK_RENDER_CNTL }
RB_RENDER_CNTL: { UNK4 | BINNING | FLAG_MRTS = 0 }
RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | BINNING | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0 }
0000000001d91370: 0000: 706d8003 00000002 00008801 00000090
t4 write GRAS_SC_WINDOW_SCISSOR_TL (80f0)
GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
@ -361,7 +361,7 @@ t7 opcode: CP_SET_MODE (63) (2 dwords)
t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
0000000001d913c8: 0000: 70268000
t4 write VFD_MODE_CNTL (a007)
VFD_MODE_CNTL: { BINNING_PASS }
VFD_MODE_CNTL: { RENDER_MODE = BINNING_PASS }
0000000001d913cc: 0000: 40a00701 00000001
t4 write VSC_BIN_SIZE (0c02)
VSC_BIN_SIZE: { WIDTH = 544 | HEIGHT = 480 }
@ -419,11 +419,11 @@ t4 write VSC_DRAW_STRM_ADDRESS (0c34)
VSC_DRAW_STRM_PITCH: 0x440
VSC_DRAW_STRM_LIMIT: 0xa000
0000000001d91484: 0000: 400c3404 01d5d000 00000000 00000440 0000a000
t4 write PC_UNKNOWN_9805 (9805)
PC_UNKNOWN_9805: 0x1
t4 write PC_POWER_CNTL (9805)
PC_POWER_CNTL: 0x1
0000000001d91498: 0000: 40980501 00000001
t4 write SP_UNKNOWN_A0F8 (a0f8)
SP_UNKNOWN_A0F8: 0x1
t4 write VFD_POWER_CNTL (a0f8)
VFD_POWER_CNTL: 0x1
0000000001d914a0: 0000: 40a0f801 00000001
t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = UNK_2C }
@ -613,7 +613,7 @@ t4 write SP_UNKNOWN_A9A8 (a9a8)
SP_UNKNOWN_A9A8: 0
0000000001121010: 0000: 40a9a801 00000000
t4 write SP_MODE_CONTROL (ab00)
SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | UNK2 }
SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
0000000001121018: 0000: 40ab0001 00000005
t4 write SP_FS_OUTPUT_CNTL0 (a98c)
SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }
@ -687,7 +687,7 @@ t4 write HLSQ_CONTROL_1_REG (b982)
HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x }
HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x }
HLSQ_CONTROL_5_REG: { UNK0 = r63.x }
HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
00000000011210a0: 0000: 40b98285 00000007 fcfcfcfc fcfcfcfc fcfcfcfc 000000fc
t4 write HLSQ_FS_CNTL_0 (b980)
HLSQ_FS_CNTL_0: { THREADSIZE = THREAD128 }
@ -706,13 +706,13 @@ t4 write GRAS_CNTL (8005)
00000000011210d8: 0000: 40800501 00000000
t4 write RB_RENDER_CONTROL0 (8809)
RB_RENDER_CONTROL0: { COORD_MASK = 0 }
RB_RENDER_CONTROL1: { 0 }
RB_RENDER_CONTROL1: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
00000000011210e0: 0000: 48880902 00000000 00000000
t4 write RB_SAMPLE_CNTL (8810)
RB_SAMPLE_CNTL: { 0 }
00000000011210ec: 0000: 40881001 00000000
t4 write GRAS_UNKNOWN_8101 (8101)
GRAS_UNKNOWN_8101: 0
t4 write GRAS_LRZ_PS_INPUT_CNTL (8101)
GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
00000000011210f4: 0000: 40810101 00000000
t4 write GRAS_SAMPLE_CNTL (8109)
GRAS_SAMPLE_CNTL: { 0 }
@ -939,10 +939,10 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+ 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
+ 00000000 GRAS_SU_POLY_OFFSET_OFFSET_CLAMP: 0.000000
+ 00000000 GRAS_SU_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
+ 00000000 GRAS_UNKNOWN_8099: 0
+ 00000000 GRAS_SU_CONSERVATIVE_RAS_CNTL: { SHIFTAMOUNT = 0 }
+ 00000000 GRAS_VS_LAYER_CNTL: { 0 }
!+ 00000002 GRAS_UNKNOWN_80A0: 0x2
!+ 06041e11 GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | BINNING_PASS | UNK22 = 0x18 }
!+ 00000002 GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = 0 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD }
!+ 06041e11 GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = BINNING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
+ 00000000 GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
!+ 00000004 GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
+ 00000000 GRAS_SAMPLE_CONFIG: { 0 }
@ -956,7 +956,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+ 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+ 059f086f GRAS_SC_WINDOW_SCISSOR_BR: { X = 2159 | Y = 1439 }
+ 00000000 GRAS_LRZ_CNTL: { 0 }
+ 00000000 GRAS_UNKNOWN_8101: 0
+ 00000000 GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
+ 00000000 GRAS_LRZ_BUFFER_BASE: 0
+ 00000000 GRAS_LRZ_BUFFER_BASE_HI: 0
+ 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
@ -966,16 +966,16 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
!+ 00000002 GRAS_UNKNOWN_8110: 0x2
+ 00000000 GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 }
!+ 059f086f GRAS_2D_RESOLVE_CNTL_2: { X = 2159 | Y = 1439 }
!+ 00000880 GRAS_UNKNOWN_8600: 0x880
!+ 06041e11 RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | BINNING_PASS | UNK22 = 0x18 }
!+ 00000090 RB_RENDER_CNTL: { UNK4 | BINNING | FLAG_MRTS = 0 }
!+ 00000880 GRAS_DBG_ECO_CNTL: { UNK7 | LRZCACHELOCKDIS }
!+ 06041e11 RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = BINNING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
!+ 00000090 RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | BINNING | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0 }
+ 00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
!+ 00000004 RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
+ 00000000 RB_SAMPLE_CONFIG: { 0 }
+ 00000000 RB_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
+ 00000000 RB_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
+ 00000000 RB_RENDER_CONTROL0: { COORD_MASK = 0 }
+ 00000000 RB_RENDER_CONTROL1: { 0 }
+ 00000000 RB_RENDER_CONTROL1: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
!+ 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
+ 00000000 RB_SRGB_CNTL: { 0 }
+ 00000000 RB_SAMPLE_CNTL: { 0 }
@ -1024,7 +1024,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+ 00000000 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
!+ 00000001 RB_UNKNOWN_8E01: 0x1
+ 00000000 RB_UNKNOWN_8E04: 0
!+ 7c400004 RB_CCU_CNTL: { COLOR_OFFSET = 0xf8000 | GMEM | UNK2 }
!+ 7c400004 RB_CCU_CNTL: { COLOR_OFFSET = 0xf8000 | DEPTH_OFFSET = 0 | GMEM | UNK2 }
!+ 00ffff00 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
!+ 0000ffff VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 }
+ 00000000 VPC_UNKNOWN_9107: { 0 }
@ -1045,7 +1045,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+ 00000000 VPC_UNKNOWN_9602: FALSE
!+ ffffffff PC_RESTART_INDEX: 4294967295
!+ 0000001f PC_MODE_CNTL: 0x1f
!+ 00000001 PC_UNKNOWN_9805: 0x1
!+ 00000001 PC_POWER_CNTL: 0x1
+ 00000000 PC_PRIMID_PASSTHRU: FALSE
+ 00000000 PC_RASTER_CNTL: { STREAM = 0 }
!+ 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
@ -1063,7 +1063,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
!+ 000000fc VFD_CONTROL_4: { UNK0 = r63.x }
!+ 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x }
+ 00000000 VFD_CONTROL_6: { 0 }
!+ 00000001 VFD_MODE_CNTL: { BINNING_PASS }
!+ 00000001 VFD_MODE_CNTL: { RENDER_MODE = BINNING_PASS }
+ 00000000 VFD_MULTIVIEW_CNTL: { VIEWS = 0 }
!+ 00000001 VFD_ADD_OFFSET: { VERTEX }
+ 00000000 VFD_INDEX_OFFSET: 0
@ -1075,7 +1075,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
!+ c7400000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT }
!+ 00000001 VFD_DECODE[0].STEP_RATE: 1
!+ 0000000f VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x }
!+ 00000001 SP_UNKNOWN_A0F8: 0x1
!+ 00000001 VFD_POWER_CNTL: 0x1
!+ 80100080 SP_VS_CTRL_REG0: { MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | 0x80000000 }
!+ 00000001 SP_VS_PRIMITIVE_CNTL: { OUT = 1 | FLAGS_REGID = r0.x }
!+ 00000f00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
@ -1119,11 +1119,11 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
!+ 00000031 SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_X8_UNORM }
!+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | UNK12 = 0x7 }
+ 00000000 SP_UNKNOWN_A9A8: 0
!+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | UNK2 }
!+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
!+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_IBO_COUNT: 0
+ 00000000 SP_UNKNOWN_AE00: 0
!+ 00001430 SP_UNKNOWN_AE03: 0x1430
!+ 00001430 SP_CHICKEN_BITS: 0x1430
!+ 00000008 SP_FLOAT_CNTL: { F16_NO_INF }
!+ 0000003f SP_PERFCTR_ENABLE: { VS | HS | DS | GS | FS | CS }
+ 00000000 SP_UNKNOWN_B182: 0
@ -1132,7 +1132,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
!+ 00000004 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
+ 00000000 SP_TP_SAMPLE_CONFIG: { 0 }
+ 00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 }
!+ 000000a2 SP_TP_UNKNOWN_B309: 162
!+ 000000a2 SP_TP_MODE_CNTL: { ISAMMODE = ISAMMODE_GL | UNK3 = 0x28 }
!+ 00100000 TPL1_UNKNOWN_B600: 0x100000
!+ 00000044 TPL1_UNKNOWN_B605: 68
!+ 00000100 HLSQ_VS_CNTL: { CONSTLEN = 0 | ENABLED }
@ -1144,7 +1144,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
!+ fcfcfcfc HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x }
!+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
!+ fcfcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x }
!+ 000000fc HLSQ_CONTROL_5_REG: { UNK0 = r63.x }
!+ 000000fc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
!+ 000000ff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
!+ 00000108 HLSQ_FS_CNTL: { CONSTLEN = 32 | ENABLED }
+ 00000000 HLSQ_SHARED_CONSTS: { 0 }
@ -1517,34 +1517,34 @@ t7 opcode: CP_SET_MODE (63) (2 dwords)
t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
0000000001d91938: 0000: 70268000
t4 write RB_CCU_CNTL (8e07)
RB_CCU_CNTL: { COLOR_OFFSET = 0xf8000 | GMEM | UNK2 }
RB_CCU_CNTL: { COLOR_OFFSET = 0xf8000 | DEPTH_OFFSET = 0 | GMEM | UNK2 }
0000000001d9193c: 0000: 408e0701 7c400004
t4 write VPC_SO_DISABLE (9306)
VPC_SO_DISABLE: { DISABLE }
0000000001d91944: 0000: 48930601 00000001
t4 write GRAS_BIN_CONTROL (80a1)
GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | USE_VIZ | UNK22 = 0x18 }
GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | FORCE_LRZ_WRITE_DIS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
0000000001d9194c: 0000: 4880a101 06201e11
t4 write RB_BIN_CONTROL (8800)
RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | USE_VIZ | UNK22 = 0x18 }
RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | FORCE_LRZ_WRITE_DIS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
0000000001d91954: 0000: 48880001 06201e11
t4 write RB_BIN_CONTROL2 (88d3)
RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 }
0000000001d9195c: 0000: 4088d301 00001e11
t4 write VFD_MODE_CNTL (a007)
VFD_MODE_CNTL: { 0 }
VFD_MODE_CNTL: { RENDER_MODE = RENDERING_PASS }
0000000001d91964: 0000: 40a00701 00000000
t4 write PC_UNKNOWN_9805 (9805)
PC_UNKNOWN_9805: 0x1
t4 write PC_POWER_CNTL (9805)
PC_POWER_CNTL: 0x1
0000000001d9196c: 0000: 40980501 00000001
t4 write SP_UNKNOWN_A0F8 (a0f8)
SP_UNKNOWN_A0F8: 0x1
t4 write VFD_POWER_CNTL (a0f8)
VFD_POWER_CNTL: 0x1
0000000001d91974: 0000: 40a0f801 00000001
t7 opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
0000000001d9197c: 0000: 709d0001 00000001
t7 opcode: CP_REG_WRITE (6d) (4 dwords)
{ TRACKER = TRACK_RENDER_CNTL }
RB_RENDER_CNTL: { UNK4 | FLAG_MRTS = 0 }
RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0 }
0000000001d91984: 0000: 706d8003 00000002 00008801 00000010
t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
0000000001d91994: 0000: 70268000
@ -1606,10 +1606,10 @@ t4 write SP_TP_WINDOW_OFFSET (b307)
SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 }
0000000001d91a38: 0000: 48b30701 00000000
t4 write GRAS_BIN_CONTROL (80a1)
GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 }
GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
0000000001d91a40: 0000: 4880a101 06001e11
t4 write RB_BIN_CONTROL (8800)
RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 }
RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
0000000001d91a48: 0000: 48880001 06001e11
t4 write RB_BIN_CONTROL2 (88d3)
RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 }
@ -1673,14 +1673,14 @@ t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
:0,1,15,5
!+ 00000005 CP_SCRATCH[0x7].REG: 5
:0,1,15,5
!+ 06001e11 GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 }
!+ 06001e11 GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
+ 00000000 GRAS_SAMPLE_CONFIG: { 0 }
+ 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+ 01df021f GRAS_SC_WINDOW_SCISSOR_BR: { X = 543 | Y = 479 }
+ 00000000 GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 }
!+ 01df021f GRAS_2D_RESOLVE_CNTL_2: { X = 543 | Y = 479 }
!+ 06001e11 RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 }
!+ 00000010 RB_RENDER_CNTL: { UNK4 | FLAG_MRTS = 0 }
!+ 06001e11 RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
!+ 00000010 RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0 }
+ 00000000 RB_SAMPLE_CONFIG: { 0 }
+ 00000000 RB_WINDOW_OFFSET: { X = 0 | Y = 0 }
+ 00000000 RB_UNKNOWN_88D0: { 0 }
@ -1695,11 +1695,11 @@ t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
+ 00000000 RB_BLIT_CLEAR_COLOR_DW2: 0
+ 00000000 RB_BLIT_CLEAR_COLOR_DW3: 0
!+ 000000f2 RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf }
+ 7c400004 RB_CCU_CNTL: { COLOR_OFFSET = 0xf8000 | GMEM | UNK2 }
+ 7c400004 RB_CCU_CNTL: { COLOR_OFFSET = 0xf8000 | DEPTH_OFFSET = 0 | GMEM | UNK2 }
!+ 00000001 VPC_SO_DISABLE: { DISABLE }
+ 00000001 PC_UNKNOWN_9805: 0x1
!+ 00000000 VFD_MODE_CNTL: { 0 }
+ 00000001 SP_UNKNOWN_A0F8: 0x1
+ 00000001 PC_POWER_CNTL: 0x1
!+ 00000000 VFD_MODE_CNTL: { RENDER_MODE = RENDERING_PASS }
+ 00000001 VFD_POWER_CNTL: 0x1
+ 00000000 SP_TP_SAMPLE_CONFIG: { 0 }
+ 00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 }
+ 00000000 SP_WINDOW_OFFSET: { X = 0 | Y = 0 }
@ -1907,7 +1907,7 @@ t4 write SP_UNKNOWN_A9A8 (a9a8)
SP_UNKNOWN_A9A8: 0
0000000001120010: 0000: 40a9a801 00000000
t4 write SP_MODE_CONTROL (ab00)
SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | UNK2 }
SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
0000000001120018: 0000: 40ab0001 00000005
t4 write SP_FS_OUTPUT_CNTL0 (a98c)
SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }
@ -1981,7 +1981,7 @@ t4 write HLSQ_CONTROL_1_REG (b982)
HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x }
HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r4.w | ZWCOORDREGID = r5.y }
HLSQ_CONTROL_5_REG: { UNK0 = r63.x }
HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
00000000011200a0: 0000: 40b98285 00000007 fcfcfcfc fcfcfcfc 1513fcfc 000000fc
t4 write HLSQ_FS_CNTL_0 (b980)
HLSQ_FS_CNTL_0: { THREADSIZE = THREAD128 }
@ -2000,13 +2000,13 @@ t4 write GRAS_CNTL (8005)
00000000011200d8: 0000: 40800501 000003c8
t4 write RB_RENDER_CONTROL0 (8809)
RB_RENDER_CONTROL0: { SIZE | COORD_MASK = 0xf }
RB_RENDER_CONTROL1: { 0 }
RB_RENDER_CONTROL1: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
00000000011200e0: 0000: 48880902 000003c8 00000000
t4 write RB_SAMPLE_CNTL (8810)
RB_SAMPLE_CNTL: { 0 }
00000000011200ec: 0000: 40881001 00000000
t4 write GRAS_UNKNOWN_8101 (8101)
GRAS_UNKNOWN_8101: 0
t4 write GRAS_LRZ_PS_INPUT_CNTL (8101)
GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
00000000011200f4: 0000: 40810101 00000000
t4 write GRAS_SAMPLE_CNTL (8109)
GRAS_SAMPLE_CNTL: { 0 }
@ -5193,10 +5193,10 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+ 059f086f GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 2159 | Y = 1439 }
+ 00000000 GRAS_SC_VIEWPORT_SCISSOR[0].TL: { X = 0 | Y = 0 }
+ 059f086f GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 2159 | Y = 1439 }
+ 00000000 GRAS_UNKNOWN_8101: 0
+ 00000000 GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
+ 00000000 GRAS_SAMPLE_CNTL: { 0 }
!+ 000003c8 RB_RENDER_CONTROL0: { SIZE | COORD_MASK = 0xf }
+ 00000000 RB_RENDER_CONTROL1: { 0 }
+ 00000000 RB_RENDER_CONTROL1: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
+ 00000000 RB_FS_OUTPUT_CNTL0: { 0 }
!+ 00000001 RB_FS_OUTPUT_CNTL1: { MRT = 1 }
!+ 00005555 RB_DITHER_CNTL: { DITHER_MODE_MRT0 = DITHER_ALWAYS | DITHER_MODE_MRT1 = DITHER_ALWAYS | DITHER_MODE_MRT2 = DITHER_ALWAYS | DITHER_MODE_MRT3 = DITHER_ALWAYS | DITHER_MODE_MRT4 = DITHER_ALWAYS | DITHER_MODE_MRT5 = DITHER_ALWAYS | DITHER_MODE_MRT6 = DITHER_ALWAYS | DITHER_MODE_MRT7 = DITHER_ALWAYS }
@ -6741,7 +6741,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
!+ 00000004 SP_FS_OUTPUT[0x7].REG: { REGID = r1.x }
+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | UNK12 = 0x7 }
+ 00000000 SP_UNKNOWN_A9A8: 0
+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | UNK2 }
+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 00000058 SP_FS_INSTRLEN: 88
!+ 011160a0 SP_IBO: 0x11160a0 base=1116000, offset=160, size=388
@ -6756,7 +6756,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+ fcfcfcfc HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x }
+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
!+ 1513fcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r4.w | ZWCOORDREGID = r5.y }
+ 000000fc HLSQ_CONTROL_5_REG: { UNK0 = r63.x }
+ 000000fc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
+ 000000ff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
+ 00000108 HLSQ_FS_CNTL: { CONSTLEN = 32 | ENABLED }
0000000001d8f130: 0000: 70388003 00000186 00000001 00000004
@ -6933,10 +6933,10 @@ t4 write SP_TP_WINDOW_OFFSET (b307)
SP_TP_WINDOW_OFFSET: { X = 544 | Y = 0 }
0000000001d91c04: 0000: 48b30701 00000220
t4 write GRAS_BIN_CONTROL (80a1)
GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 }
GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
0000000001d91c0c: 0000: 4880a101 06001e11
t4 write RB_BIN_CONTROL (8800)
RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 }
RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
0000000001d91c14: 0000: 48880001 06001e11
t4 write RB_BIN_CONTROL2 (88d3)
RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 }
@ -7102,10 +7102,10 @@ t4 write SP_TP_WINDOW_OFFSET (b307)
SP_TP_WINDOW_OFFSET: { X = 1088 | Y = 0 }
0000000001d91dd0: 0000: 48b30701 00000440
t4 write GRAS_BIN_CONTROL (80a1)
GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 }
GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
0000000001d91dd8: 0000: 4880a101 06001e11
t4 write RB_BIN_CONTROL (8800)
RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 }
RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
0000000001d91de0: 0000: 48880001 06001e11
t4 write RB_BIN_CONTROL2 (88d3)
RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 }
@ -7271,10 +7271,10 @@ t4 write SP_TP_WINDOW_OFFSET (b307)
SP_TP_WINDOW_OFFSET: { X = 1632 | Y = 0 }
0000000001d91f9c: 0000: 48b30701 00000660
t4 write GRAS_BIN_CONTROL (80a1)
GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 }
GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
0000000001d91fa4: 0000: 4880a101 06001e11
t4 write RB_BIN_CONTROL (8800)
RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 }
RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
0000000001d91fac: 0000: 48880001 06001e11
t4 write RB_BIN_CONTROL2 (88d3)
RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 }

3
src/freedreno/common/freedreno_dev_info.h
View File

@ -99,8 +99,7 @@ struct fd_dev_info {
struct {
uint32_t RB_UNKNOWN_8E04_blit;
uint32_t PC_UNKNOWN_9805;
uint32_t SP_UNKNOWN_A0F8;
uint32_t PC_POWER_CNTL;
} magic;
} a6xx;
};

24
src/freedreno/common/freedreno_devices.py
View File

@ -109,8 +109,7 @@ class A6xxGPUInfo(GPUInfo):
duplication of parameters that are unique to the sub-generation.
"""
def __init__(self, template, num_sp_cores, num_ccu,
RB_UNKNOWN_8E04_blit, PC_UNKNOWN_9805,
SP_UNKNOWN_A0F8):
RB_UNKNOWN_8E04_blit, PC_POWER_CNTL):
super().__init__(gmem_align_w = 16, gmem_align_h = 4,
tile_align_w = 32, tile_align_h = 32,
tile_max_w = 1024, # max_bitfield_val(5, 0, 5)
@ -129,8 +128,7 @@ class A6xxGPUInfo(GPUInfo):
# Various "magic" register values:
self.a6xx.magic.RB_UNKNOWN_8E04_blit = RB_UNKNOWN_8E04_blit
self.a6xx.magic.PC_UNKNOWN_9805 = PC_UNKNOWN_9805
self.a6xx.magic.SP_UNKNOWN_A0F8 = SP_UNKNOWN_A0F8
self.a6xx.magic.PC_POWER_CNTL = PC_POWER_CNTL
# Things that earlier gens have and later gens remove, provide
# defaults here and let them be overridden by sub-gen template:
@ -247,8 +245,7 @@ add_gpus([
num_sp_cores = 1,
num_ccu = 1,
RB_UNKNOWN_8E04_blit = 0x00100000,
PC_UNKNOWN_9805 = 0,
SP_UNKNOWN_A0F8 = 0,
PC_POWER_CNTL = 0,
))
add_gpus([
@ -258,8 +255,7 @@ add_gpus([
num_sp_cores = 2,
num_ccu = 2,
RB_UNKNOWN_8E04_blit = 0x01000000,
PC_UNKNOWN_9805 = 1,
SP_UNKNOWN_A0F8 = 1,
PC_POWER_CNTL = 1,
))
add_gpus([
@ -269,8 +265,7 @@ add_gpus([
num_sp_cores = 2,
num_ccu = 2,
RB_UNKNOWN_8E04_blit = 0x00100000,
PC_UNKNOWN_9805 = 1,
SP_UNKNOWN_A0F8 = 1,
PC_POWER_CNTL = 1,
))
add_gpus([
@ -280,8 +275,7 @@ add_gpus([
num_sp_cores = 3,
num_ccu = 3,
RB_UNKNOWN_8E04_blit = 0x04100000,
PC_UNKNOWN_9805 = 2,
SP_UNKNOWN_A0F8 = 2,
PC_POWER_CNTL = 2,
))
add_gpus([
@ -291,8 +285,7 @@ add_gpus([
num_sp_cores = 2,
num_ccu = 2,
RB_UNKNOWN_8E04_blit = 0x00100000,
PC_UNKNOWN_9805 = 1,
SP_UNKNOWN_A0F8 = 1,
PC_POWER_CNTL = 1,
))
add_gpus([
@ -302,8 +295,7 @@ add_gpus([
num_sp_cores = 3,
num_ccu = 3,
RB_UNKNOWN_8E04_blit = 0x04100000,
PC_UNKNOWN_9805 = 2,
SP_UNKNOWN_A0F8 = 2,
PC_POWER_CNTL = 2,
))
template = """\

2
src/freedreno/decode/cffdec.c
View File

@ -2418,7 +2418,7 @@ cp_exec_cs_indirect(uint32_t *dwords, uint32_t sizedwords, int level)
static void
cp_set_marker(uint32_t *dwords, uint32_t sizedwords, int level)
{
render_mode = rnn_enumname(rnn, "a6xx_render_mode", dwords[0] & 0xf);
render_mode = rnn_enumname(rnn, "a6xx_marker", dwords[0] & 0xf);
if (!strcmp(render_mode, "RM6_BINNING")) {
enable_mask = MODE_BINNING;

171
src/freedreno/registers/adreno/a6xx.xml
View File

@ -1446,6 +1446,7 @@ to upconvert to 32b float internally?
<reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/>
<reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/>
<reg32 offset="0x0c00" name="VSC_DBG_ECO_CNTL"/>
<reg32 offset="0x0c02" name="VSC_BIN_SIZE">
<bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
<bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
@ -1618,8 +1619,16 @@ to upconvert to 32b float internally?
<bitfield name="UNK3" pos="3"/>
</reg32>
<reg32 offset="0x8099" name="GRAS_UNKNOWN_8099" low="0" high="5"/>
<reg32 offset="0x809a" name="GRAS_UNKNOWN_809A" low="0" high="1"/>
<reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL">
<bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>
<bitfield name="SHIFTAMOUNT" low="1" high="2"/>
<bitfield name="INNERCONSERVATIVERASEN" pos="3" type="boolean"/>
<bitfield name="UNK4" low="4" high="5"/>
</reg32>
<reg32 offset="0x809a" name="GRAS_SU_PATH_RENDERING_CNTL">
<bitfield name="UNK0" pos="0" type="boolean"/>
<bitfield name="LINELENGTHEN" pos="1" type="boolean"/>
</reg32>
<bitset name="a6xx_gras_layer_cntl" inline="yes">
<bitfield name="WRITES_LAYER" pos="0" type="boolean"/>
@ -1629,15 +1638,59 @@ to upconvert to 32b float internally?
<reg32 offset="0x809c" name="GRAS_GS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
<reg32 offset="0x809d" name="GRAS_DS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
<!-- 0x809e/0x809f invalid -->
<reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0" low="0" high="12"/>
<enum name="a6xx_sequenced_thread_dist">
<value value="0x0" name="DIST_SCREEN_COORD"/>
<value value="0x1" name="DIST_ALL_TO_RB0"/>
</enum>
<enum name="a6xx_single_prim_mode">
<value value="0x3" name="FLUSH_PER_OVERLAP"/>
</enum>
<!-- this probably has the same meaning as a3xx GRAS_SC_CONTROL::RASTER_MODE -->
<enum name="a6xx_raster_mode">
<value value="0x0" name="TYPE_TILED"/>
<value value="0x1" name="TYPE_WRITER"/>
</enum>
<!-- I'm guessing this is the same as a3xx -->
<enum name="a6xx_raster_direction">
<value value="0x0" name="LR_TB"/>
<value value="0x1" name="RL_TB"/>
<value value="0x2" name="LR_BT"/>
<value value="0x3" name="RB_BT"/>
</enum>
<reg32 offset="0x80a0" name="GRAS_SC_CNTL">
<bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2"/>
<bitfield name="SINGLE_PRIM_MODE" low="3" high="4" type="a6xx_single_prim_mode"/>
<bitfield name="RASTER_MODE" pos="5" type="a6xx_raster_mode"/>
<bitfield name="RASTER_DIRECTION" low="6" high="7" type="a6xx_raster_direction"/>
<bitfield name="SEQUENCED_THREAD_DISTRIBUTION" pos="8" type="a6xx_sequenced_thread_dist"/>
<!-- CCUSINGLECACHELINESIZE is ignored unless bit 9 is set -->
<bitfield name="UNK9" low="9" high="11"/>
<bitfield name="EARLYVIZOUTEN" pos="12" type="boolean"/>
</reg32>
<enum name="a6xx_render_mode">
<value value="0x0" name="RENDERING_PASS"/>
<value value="0x1" name="BINNING_PASS"/>
</enum>
<enum name="a6xx_buffers_location">
<value value="0" name="BUFFERS_IN_GMEM"/>
<value value="3" name="BUFFERS_IN_SYSMEM"/>
</enum>
<reg32 offset="0x80a1" name="GRAS_BIN_CONTROL">
<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
<bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
<bitfield name="BINNING_PASS" pos="18" type="boolean"/>
<bitfield name="UNK19" pos="19"/>
<bitfield name="UNK20" pos="20"/>
<bitfield name="USE_VIZ" pos="21" type="boolean"/>
<bitfield name="UNK22" low="22" high="27"/>
<bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
<bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>
<bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location"/>
<bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26"/>
<bitfield name="UNK27" pos="27"/>
</reg32>
<reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL">
@ -1705,7 +1758,17 @@ to upconvert to 32b float internally?
<bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/>
<bitfield name="UNK6" low="6" high="9"/>
</reg32>
<reg32 offset="0x8101" name="GRAS_UNKNOWN_8101" low="0" high="2"/>
<enum name="a6xx_fragcoord_sample_mode">
<value value="0" name="FRAGCOORD_CENTER"/>
<value value="3" name="FRAGCOORD_SAMPLE"/>
</enum>
<reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" low="0" high="2">
<bitfield name="SAMPLEID" pos="0" type="boolean"/>
<bitfield name="FRAGCOORDSAMPLEMODE" low="1" high="2" type="a6xx_fragcoord_sample_mode"/>
</reg32>
<reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO">
<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
</reg32>
@ -1774,7 +1837,8 @@ to upconvert to 32b float internally?
<bitset name="a6xx_2d_blit_cntl" inline="yes">
<bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
<bitfield name="UNK3" low="3" high="6"/>
<bitfield name="OVERWRITEEN" pos="3" type="boolean"/>
<bitfield name="UNK4" low="4" high="6"/>
<bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
<bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/>
<bitfield name="SCISSOR" pos="16" type="boolean"/>
@ -1784,7 +1848,7 @@ to upconvert to 32b float internally?
<!-- some sort of channel mask, disabled channels are set to zero ? -->
<bitfield name="MASK" low="20" high="23"/>
<bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
<bitfield name="UNK29" pos="29"/>
<bitfield name="RASTER_MODE" pos="29" type="a6xx_raster_mode"/>
</bitset>
<reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
@ -1806,7 +1870,10 @@ to upconvert to 32b float internally?
<!-- 0x840c-0x85ff invalid -->
<!-- always 0x880 ? (and 0 in a640/a650 traces?) -->
<reg32 offset="0x8600" name="GRAS_UNKNOWN_8600" low="0" high="12" />
<reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL">
<bitfield name="UNK7" pos="7" type="boolean"/>
<bitfield name="LRZCACHELOCKDIS" pos="11" type="boolean"/>
</reg32>
<reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
<array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4"/>
<array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4"/>
@ -1820,20 +1887,22 @@ to upconvert to 32b float internally?
<reg32 offset="0x8800" name="RB_BIN_CONTROL">
<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
<bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
<bitfield name="BINNING_PASS" pos="18" type="boolean"/>
<bitfield name="UNK19" pos="19"/>
<bitfield name="UNK20" pos="20"/>
<bitfield name="USE_VIZ" pos="21" type="boolean"/>
<bitfield name="UNK22" low="22" high="26"/>
<bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
<bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>
<bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location"/>
<bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26"/>
</reg32>
<reg32 offset="0x8801" name="RB_RENDER_CNTL">
<bitfield name="UNK3" pos="3" type="boolean"/>
<!-- always set: ?? -->
<bitfield name="UNK4" pos="4" type="boolean"/>
<bitfield name="UNK5" low="5" high="6"/>
<bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/>
<bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/>
<!-- set during binning pass: -->
<bitfield name="BINNING" pos="7" type="boolean"/>
<bitfield name="UNK8" low="8" high="12"/>
<bitfield name="UNK8" low="8" high="10"/>
<bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/>
<bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/>
<bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/>
<bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/>
<!-- bit seems to be set whenever depth buffer enabled: -->
<bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
<!-- bitmask of MRTs using UBWC flag buffer: -->
@ -1881,12 +1950,10 @@ to upconvert to 32b float internally?
<bitfield name="UNK1" pos="1" type="boolean"/>
<bitfield name="FACENESS" pos="2" type="boolean"/>
<bitfield name="SAMPLEID" pos="3" type="boolean"/>
<!-- b4 and b5 set in per-sample mode: -->
<bitfield name="UNK4" pos="4" type="boolean"/>
<bitfield name="UNK5" pos="5" type="boolean"/>
<bitfield name="FRAGCOORDSAMPLEMODE" low="4" high="5" type="a6xx_fragcoord_sample_mode"/>
<bitfield name="SIZE" pos="6" type="boolean"/>
<bitfield name="UNK7" pos="7" type="boolean"/>
<bitfield name="UNK8" pos="8" type="boolean"/>
<bitfield name="LINELENGTHEN" pos="7" type="boolean"/>
<bitfield name="FOVEATION" pos="8" type="boolean"/>
</reg32>
<reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0">
@ -2230,14 +2297,14 @@ to upconvert to 32b float internally?
<!-- 0x8e06 invalid -->
<reg32 offset="0x8e07" name="RB_CCU_CNTL">
<!-- GMEM offset of CCU color cache
CCU depth cache starts at zero, so this should be the size
of the depth cache for direct rendering
for GMEM rendering, we set it to GMEM size minus the minimum
CCU color cache size. CCU color cache will be needed in some
resolve cases, and in those cases we need to reserve the end
of GMEM for color cache.
-->
<bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/>
<!-- GMEM offset of CCU depth cache -->
<bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/>
<bitfield name="GMEM" pos="22" type="boolean"/> <!-- set for GMEM path -->
<bitfield name="UNK2" pos="2" type="boolean"/> <!-- sometimes set with GMEM? -->
<!--TODO: valid mask 0xfffffc1f -->
@ -2273,8 +2340,9 @@ to upconvert to 32b float internally?
<!-- 0x9000-0x90ff invalid -->
<!-- something to do with geometry shader: -->
<reg32 offset="0x9100" name="VPC_UNKNOWN_9100" low="0" high="7"/>
<reg32 offset="0x9100" name="VPC_GS_PARAM">
<bitfield name="LINELENGTHLOC" low="0" high="7" type="uint"/>
</reg32>
<bitset name="a6xx_vpc_xs_clip_cntl" inline="yes">
<bitfield name="CLIP_MASK" low="0" high="7" type="uint"/>
@ -2470,11 +2538,14 @@ to upconvert to 32b float internally?
<reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint"/>
<reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7"/>
<!-- always 0x1 ? -->
<reg32 offset="0x9805" name="PC_UNKNOWN_9805" low="0" high="2"/>
<reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2"/>
<!-- probably a mirror of VFD_CONTROL_6 -->
<reg32 offset="0x9806" name="PC_PRIMID_PASSTHRU" pos="0" type="boolean"/>
<reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL">
<bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>
</reg32>
<!-- 0x980b-0x983f invalid -->
<!-- 0x9840 - 0x9842 are not readable -->
@ -2550,6 +2621,7 @@ to upconvert to 32b float internally?
<!-- TODO: first 16 bits are valid so something is wrong or missing here -->
<bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
<bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
<bitfield name="LINELENGTHEN" pos="15" type="boolean"/>
<bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
<bitfield name="UNK18" pos="18"/>
</reg32>
@ -2668,9 +2740,7 @@ to upconvert to 32b float internally?
</reg32>
<reg32 offset="0xa007" name="VFD_MODE_CNTL">
<bitfield name="BINNING_PASS" pos="0" type="boolean"/>
<bitfield name="UNK1" pos="1" type="boolean"/>
<bitfield name="UNK2" pos="2" type="boolean"/>
<bitfield name="RENDER_MODE" low="0" high="2" type="a6xx_render_mode"/>
</reg32>
<reg32 offset="0xa008" name="VFD_MULTIVIEW_CNTL" type="a6xx_multiview_cntl"/>
@ -2708,8 +2778,7 @@ to upconvert to 32b float internally?
</reg32>
</array>
<!-- 0 on 618, 1 on 630/640, 2 on a650? (SP count - 1) ? -->
<reg32 offset="0xa0f8" name="SP_UNKNOWN_A0F8" low="0" high="2"/>
<reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2"/>
<!--
Note: this seems to always be paired with another bit in another
@ -3187,6 +3256,16 @@ to upconvert to 32b float internally?
<reg64 offset="0xa9f2" name="SP_CS_IBO" type="address" align="16"/>
<reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" low="0" high="6" type="uint"/>
<!--
This enum is probably similar in purpose to SNORMMODE on a3xx,
minus the snorm stuff, i.e. it controls what happens with an
out-of-bounds isam/isamm. GL and Vulkan robustness require us to
return 0 on out-of-bound textureFetch().
-->
<enum name="a6xx_isam_mode">
<value value="0x2" name="ISAMMODE_GL"/>
</enum>
<reg32 offset="0xab00" name="SP_MODE_CONTROL">
<!--
When set, half register loads from the constant file will
@ -3197,8 +3276,7 @@ to upconvert to 32b float internally?
file (so hc0.y loads the top 16 bits of the value of c0.x)
-->
<bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/>
<bitfield name="UNK1" pos="1" type="boolean"/> <!-- never set by VK blob -->
<bitfield name="UNK2" pos="2" type="boolean"/> <!-- always set by VK blob -->
<bitfield name="ISAMMODE" low="1" high="2" type="a6xx_isam_mode"/>
<bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS -->
</reg32>
@ -3235,7 +3313,7 @@ to upconvert to 32b float internally?
<reg32 offset="0xae02" name="SP_NC_MODE_CNTL">
<!-- TODO: valid bits 0x3c3f, see kernel -->
</reg32>
<reg32 offset="0xae03" name="SP_UNKNOWN_AE03"/>
<reg32 offset="0xae03" name="SP_CHICKEN_BITS"/>
<reg32 offset="0xae04" name="SP_FLOAT_CNTL">
<bitfield name="F16_NO_INF" pos="3" type="boolean"/>
</reg32>
@ -3254,6 +3332,7 @@ to upconvert to 32b float internally?
<array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24"/>
<!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) -->
<!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range -->
<reg32 offset="0xbe22" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
<!--
The downstream kernel calls the debug cluster of registers
@ -3284,7 +3363,10 @@ to upconvert to 32b float internally?
<reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
<reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
<reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="a6xx_reg_xy"/>
<reg32 offset="0xb309" name="SP_TP_UNKNOWN_B309" low="0" high="7" type="uint"/>
<reg32 offset="0xb309" name="SP_TP_MODE_CNTL">
<bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/>
<bitfield name="UNK3" low="2" high="7"/>
</reg32>
<!--
Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either
@ -3388,8 +3470,8 @@ to upconvert to 32b float internally?
<bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
</reg32>
<reg32 offset="0xb986" name="HLSQ_CONTROL_5_REG">
<bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/>
<bitfield name="UNK8" low="8" high="15" type="a3xx_regid"/>
<bitfield name="LINELENGTHREGID" low="0" high="7" type="a3xx_regid"/>
<bitfield name="FOVEATIONQUALITYREGID" low="8" high="15" type="a3xx_regid"/>
</reg32>
<reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl"/>
@ -3539,6 +3621,7 @@ to upconvert to 32b float internally?
<array offset="0xbe10" name="HLSQ_PERFCTR_HLSQ_SEL" stride="1" length="6"/>
<!-- TODO: some valid registers between 0xbe20 and 0xbe33 -->
<reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
<!--
These special registers signal the beginning/end of an event

6
src/freedreno/registers/adreno/adreno_pm4.xml
View File

@ -1509,7 +1509,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
<domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
<doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
<enum name="a6xx_render_mode">
<enum name="a6xx_marker">
<value value="1" name="RM6_BYPASS"/>
<value value="2" name="RM6_BINNING"/>
<value value="4" name="RM6_GMEM"/>
@ -1540,8 +1540,8 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
model this, without getting confused by spurious b4, this is
described as two overlapping bitfields:
-->
<bitfield name="MODE" low="0" high="8" type="a6xx_render_mode"/>
<bitfield name="MARKER" low="0" high="3" type="a6xx_render_mode"/>
<bitfield name="MODE" low="0" high="8" type="a6xx_marker"/>
<bitfield name="MARKER" low="0" high="3" type="a6xx_marker"/>
</reg32>
</domain>

39
src/freedreno/vulkan/tu_cmd_buffer.c
View File

@ -336,7 +336,7 @@ tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
/* doesn't RB_RENDER_CNTL set differently for binning pass: */
bool no_track = !cmd->device->physical_device->info->a6xx.has_cp_reg_write;
uint32_t cntl = 0;
cntl |= A6XX_RB_RENDER_CNTL_UNK4;
cntl |= A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(2);
if (binning) {
if (no_track)
return;
@ -746,9 +746,9 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_DBG_ECO_CNTL, 0x880);
tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_CHICKEN_BITS, 0x00000410);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_SHARED_CONSTS, 0);
@ -782,14 +782,17 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SC_CNTL,
A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(2));
tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_MODE_CNTL,
0x000000a0 |
A6XX_SP_TP_MODE_CNTL_ISAMMODE(ISAMMODE_GL));
tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
@ -927,15 +930,15 @@ tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_cs_emit_wfi(cs);
tu_cs_emit_regs(cs,
A6XX_VFD_MODE_CNTL(.binning_pass = true));
A6XX_VFD_MODE_CNTL(.render_mode = BINNING_PASS));
update_vsc_pipe(cmd, cs);
tu_cs_emit_regs(cs,
A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->info->a6xx.magic.PC_UNKNOWN_9805));
A6XX_PC_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
tu_cs_emit_regs(cs,
A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->info->a6xx.magic.SP_UNKNOWN_A0F8));
A6XX_VFD_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
tu_cs_emit(cs, UNK_2C);
@ -1150,7 +1153,8 @@ tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu6_emit_window_scissor(cs, 0, 0, fb->width - 1, fb->height - 1);
tu6_emit_window_offset(cs, 0, 0);
tu6_emit_bin_size(cs, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
tu6_emit_bin_size(cs, 0, 0,
A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(BUFFERS_IN_SYSMEM));
tu6_emit_event_write(cmd, cs, LRZ_FLUSH);
@ -1210,7 +1214,8 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false));
tu6_emit_bin_size(cs, fb->tile0.width, fb->tile0.height,
A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
A6XX_RB_BIN_CONTROL_RENDER_MODE(BINNING_PASS) |
A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(0x6));
tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, true);
@ -1220,14 +1225,17 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true));
tu6_emit_bin_size(cs, fb->tile0.width, fb->tile0.height,
A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS |
A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(0x6));
tu_cs_emit_regs(cs,
A6XX_VFD_MODE_CNTL(0));
tu_cs_emit_regs(cs, A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->info->a6xx.magic.PC_UNKNOWN_9805));
tu_cs_emit_regs(cs,
A6XX_PC_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
tu_cs_emit_regs(cs, A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->info->a6xx.magic.SP_UNKNOWN_A0F8));
tu_cs_emit_regs(cs,
A6XX_VFD_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
tu_cs_emit(cs, 0x1);
@ -1235,7 +1243,8 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
/* no binning pass, so enable stream-out for draw pass:: */
tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false));
tu6_emit_bin_size(cs, fb->tile0.width, fb->tile0.height, 0x6000000);
tu6_emit_bin_size(cs, fb->tile0.width, fb->tile0.height,
A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(0x6));
}
tu_cs_sanity_check(cs);

14
src/freedreno/vulkan/tu_pipeline.c
View File

@ -1194,7 +1194,7 @@ tu6_emit_vpc(struct tu_cs *cs,
A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_VPC_GS_PARAM, 1);
tu_cs_emit(cs, 0xff);
tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
@ -1415,11 +1415,8 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
COND(fs->fragcoord_compmask != 0,
A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)));
tu_cs_emit(cs,
/* these two bits (UNK4/UNK5) relate to fragcoord
* without them, fragcoord is the same for all samples
*/
COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK4) |
COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK5) |
A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(
sample_shading ? FRAGCOORD_SAMPLE : FRAGCOORD_CENTER) |
CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
CONDREG(ij_regid[IJ_PERSP_SIZE], A6XX_RB_RENDER_CONTROL1_SIZE) |
@ -1428,8 +1425,9 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL, 1);
tu_cs_emit(cs, A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(
sample_shading ? FRAGCOORD_SAMPLE : FRAGCOORD_CENTER));
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));

15
src/gallium/drivers/freedreno/a6xx/fd6_emit.c
View File

@ -1247,9 +1247,9 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
WRITE(REG_A6XX_VPC_UNKNOWN_9600, 0);
WRITE(REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
WRITE(REG_A6XX_GRAS_DBG_ECO_CNTL, 0x880);
WRITE(REG_A6XX_HLSQ_UNKNOWN_BE04, 0x80000);
WRITE(REG_A6XX_SP_UNKNOWN_AE03, 0x1430);
WRITE(REG_A6XX_SP_CHICKEN_BITS, 0x1430);
WRITE(REG_A6XX_SP_IBO_COUNT, 0);
WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);
WRITE(REG_A6XX_HLSQ_SHARED_CONSTS, 0);
@ -1262,7 +1262,7 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
WRITE(REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
WRITE(REG_A6XX_PC_MODE_CNTL, 0x1f);
WRITE(REG_A6XX_GRAS_UNKNOWN_8101, 0);
WRITE(REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL, 0);
WRITE(REG_A6XX_GRAS_SAMPLE_CNTL, 0);
WRITE(REG_A6XX_GRAS_UNKNOWN_8110, 0x2);
@ -1286,19 +1286,20 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
WRITE(REG_A6XX_SP_UNKNOWN_B183, 0);
WRITE(REG_A6XX_GRAS_UNKNOWN_8099, 0);
WRITE(REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 0);
WRITE(REG_A6XX_GRAS_VS_LAYER_CNTL, 0);
WRITE(REG_A6XX_GRAS_UNKNOWN_80A0, 2);
WRITE(REG_A6XX_GRAS_SC_CNTL, A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(2));
WRITE(REG_A6XX_GRAS_UNKNOWN_80AF, 0);
WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
WRITE(REG_A6XX_SP_TP_SAMPLE_CONFIG, 0);
/* NOTE blob seems to (mostly?) use 0xb2 for SP_TP_UNKNOWN_B309
/* NOTE blob seems to (mostly?) use 0xb2 for SP_TP_MODE_CNTL
* but this seems to kill texture gather offsets.
*/
WRITE(REG_A6XX_SP_TP_UNKNOWN_B309, 0xa2);
WRITE(REG_A6XX_SP_TP_MODE_CNTL, 0xa0 |
A6XX_SP_TP_MODE_CNTL_ISAMMODE(ISAMMODE_GL));
WRITE(REG_A6XX_RB_SAMPLE_CONFIG, 0);
WRITE(REG_A6XX_GRAS_SAMPLE_CONFIG, 0);
WRITE(REG_A6XX_RB_Z_BOUNDS_MIN, 0);

30
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
View File

@ -360,7 +360,7 @@ update_render_cntl(struct fd_batch *batch, struct pipe_framebuffer_state *pfb,
mrts_ubwc_enable |= 1 << i;
}
cntl |= A6XX_RB_RENDER_CNTL_UNK4;
cntl |= A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(2);
if (binning)
cntl |= A6XX_RB_RENDER_CNTL_BINNING;
@ -689,15 +689,15 @@ emit_binning_pass(struct fd_batch *batch) assert_dt
OUT_WFI5(ring);
OUT_REG(ring, A6XX_VFD_MODE_CNTL(.binning_pass = true));
OUT_REG(ring, A6XX_VFD_MODE_CNTL(.render_mode = BINNING_PASS));
update_vsc_pipe(batch);
OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
OUT_RING(ring, screen->info->a6xx.magic.PC_UNKNOWN_9805);
OUT_PKT4(ring, REG_A6XX_PC_POWER_CNTL, 1);
OUT_RING(ring, screen->info->a6xx.magic.PC_POWER_CNTL);
OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
OUT_RING(ring, screen->info->a6xx.magic.SP_UNKNOWN_A0F8);
OUT_PKT4(ring, REG_A6XX_VFD_POWER_CNTL, 1);
OUT_RING(ring, screen->info->a6xx.magic.PC_POWER_CNTL);
OUT_PKT7(ring, CP_EVENT_WRITE, 1);
OUT_RING(ring, UNK_2C);
@ -827,7 +827,8 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
OUT_REG(ring, A6XX_VPC_SO_DISABLE(false));
set_bin_size(ring, gmem->bin_w, gmem->bin_h,
A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
A6XX_RB_BIN_CONTROL_RENDER_MODE(BINNING_PASS) |
A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(0x6));
update_render_cntl(batch, pfb, true);
emit_binning_pass(batch);
@ -840,20 +841,19 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
* the reset of these cmds:
*/
// NOTE a618 not setting .USE_VIZ .. from a quick check on a630, it
// does not appear that this bit changes much (ie. it isn't actually
// .USE_VIZ like previous gens)
// NOTE a618 not setting .FORCE_LRZ_WRITE_DIS ..
set_bin_size(ring, gmem->bin_w, gmem->bin_h,
A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS |
A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(0x6));
OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
OUT_RING(ring, 0x0);
OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
OUT_RING(ring, screen->info->a6xx.magic.PC_UNKNOWN_9805);
OUT_PKT4(ring, REG_A6XX_PC_POWER_CNTL, 1);
OUT_RING(ring, screen->info->a6xx.magic.PC_POWER_CNTL);
OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
OUT_RING(ring, screen->info->a6xx.magic.SP_UNKNOWN_A0F8);
OUT_PKT4(ring, REG_A6XX_VFD_POWER_CNTL, 1);
OUT_RING(ring, screen->info->a6xx.magic.PC_POWER_CNTL);
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
OUT_RING(ring, 0x1);

7
src/gallium/drivers/freedreno/a6xx/fd6_program.c
View File

@ -816,8 +816,9 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
OUT_RING(ring, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8101, 1);
OUT_RING(ring, COND(sample_shading, 0x6)); // XXX
OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL, 1);
OUT_RING(ring, A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(
sample_shading ? FRAGCOORD_SAMPLE : FRAGCOORD_CENTER));
OUT_PKT4(ring, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
OUT_RING(ring, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
@ -910,7 +911,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
OUT_RING(ring, A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(clip_mask) |
A6XX_GRAS_GS_CL_CNTL_CULL_MASK(cull_mask));
OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9100, 1);
OUT_PKT4(ring, REG_A6XX_VPC_GS_PARAM, 1);
OUT_RING(ring, 0xff);
OUT_PKT4(ring, REG_A6XX_VPC_GS_CLIP_CNTL, 1);