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nir: Handle vec8/16 in lower_regs_to_ssa 

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4365>
This commit is contained in:
Jason Ekstrand 2020-03-30 12:07:09 -05:00 committed by Marge Bot
parent 1033255952
commit 2aab7999e4
1 changed files with 1 additions and 7 deletions
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8
src/compiler/nir/nir_lower_regs_to_ssa.c
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@ -178,13 +178,7 @@ rewrite_alu_instr(nir_alu_instr *alu, struct regs_to_ssa_state *state)
nir_ssa_dest_init(&alu->instr, &alu->dest.dest, num_components,
reg->bit_size, reg->name);
nir_op vecN_op;
switch (reg->num_components) {
case 2: vecN_op = nir_op_vec2; break;
case 3: vecN_op = nir_op_vec3; break;
case 4: vecN_op = nir_op_vec4; break;
default: unreachable("not reached");
}
nir_op vecN_op = nir_op_vec(reg->num_components);
nir_alu_instr *vec = nir_alu_instr_create(state->shader, vecN_op);