radeonsi: inline struct r600_cmask_info
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
This commit is contained in:
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166250f4e5
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2a8d1039b6
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@ -538,7 +538,7 @@ si_decompress_color_texture(struct si_context *sctx, struct si_texture *tex,
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unsigned first_level, unsigned last_level)
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{
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/* CMASK or DCC can be discarded and we can still end up here. */
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if (!tex->cmask.size && !tex->surface.fmask_size && !tex->dcc_offset)
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if (!tex->cmask_size && !tex->surface.fmask_size && !tex->dcc_offset)
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return;
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si_blit_decompress_color(sctx, tex, first_level, last_level, 0,
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@ -859,7 +859,7 @@ static void si_decompress_subresource(struct pipe_context *ctx,
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si_decompress_depth(sctx, stex, planes,
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level, level,
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first_layer, last_layer);
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} else if (stex->surface.fmask_size || stex->cmask.size || stex->dcc_offset) {
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} else if (stex->surface.fmask_size || stex->cmask_size || stex->dcc_offset) {
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/* If we've rendered into the framebuffer and it's a blitting
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* source, make sure the decompression pass is invoked
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* by dirtying the framebuffer.
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@ -1139,7 +1139,7 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
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info->src.box.height == dst_height &&
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info->src.box.depth == 1 &&
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!dst->surface.is_linear &&
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(!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
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(!dst->cmask_size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
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/* Check the last constraint. */
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if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
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/* The next fast clear will switch to this mode to
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@ -1325,7 +1325,7 @@ static void si_flush_resource(struct pipe_context *ctx,
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if (tex->dcc_separate_buffer && !tex->separate_dcc_dirty)
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return;
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if (!tex->is_depth && (tex->cmask.size || tex->dcc_offset)) {
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if (!tex->is_depth && (tex->cmask_size || tex->dcc_offset)) {
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si_blit_decompress_color(sctx, tex, 0, res->last_level,
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0, util_max_layer(res, 0),
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tex->dcc_separate_buffer != NULL);
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@ -40,7 +40,7 @@ static void si_alloc_separate_cmask(struct si_screen *sscreen,
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if (tex->cmask_buffer)
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return;
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assert(tex->cmask.size == 0);
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assert(tex->cmask_size == 0);
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if (!tex->surface.cmask_size)
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return;
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@ -54,8 +54,8 @@ static void si_alloc_separate_cmask(struct si_screen *sscreen,
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if (tex->cmask_buffer == NULL)
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return;
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tex->cmask.size = tex->surface.cmask_size;
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tex->cmask.base_address_reg = tex->cmask_buffer->gpu_address >> 8;
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tex->cmask_size = tex->surface.cmask_size;
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tex->cmask_base_address_reg = tex->cmask_buffer->gpu_address >> 8;
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tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
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p_atomic_inc(&sscreen->compressed_colortex_counter);
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@ -490,13 +490,13 @@ static void si_do_fast_color_clear(struct si_context *sctx,
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continue;
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/* DCC fast clear with MSAA should clear CMASK to 0xC. */
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if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask.size) {
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if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_size) {
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/* TODO: This doesn't work with MSAA. */
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if (eliminate_needed)
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continue;
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si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
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tex->cmask.offset, tex->cmask.size,
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tex->cmask_offset, tex->cmask_size,
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0xCCCCCCCC, SI_COHERENCY_CB_META);
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need_decompress_pass = true;
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}
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@ -522,13 +522,13 @@ static void si_do_fast_color_clear(struct si_context *sctx,
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/* ensure CMASK is enabled */
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si_alloc_separate_cmask(sctx->screen, tex);
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if (tex->cmask.size == 0) {
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if (tex->cmask_size == 0) {
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continue;
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}
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/* Do the fast clear. */
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si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
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tex->cmask.offset, tex->cmask.size, 0,
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tex->cmask_offset, tex->cmask_size, 0,
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SI_COHERENCY_CB_META);
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need_decompress_pass = true;
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}
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@ -478,7 +478,7 @@ static bool color_needs_decompression(struct si_texture *tex)
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{
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return tex->surface.fmask_size ||
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(tex->dirty_level_mask &&
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(tex->cmask.size || tex->dcc_offset));
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(tex->cmask_size || tex->dcc_offset));
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}
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static bool depth_needs_decompression(struct si_texture *tex)
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@ -230,12 +230,6 @@ struct r600_transfer {
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unsigned offset;
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};
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struct r600_cmask_info {
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uint64_t offset;
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uint64_t base_address_reg;
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uint32_t size;
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};
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struct si_texture {
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struct r600_resource buffer;
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@ -245,7 +239,9 @@ struct si_texture {
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/* Colorbuffer compression and fast clear. */
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uint64_t fmask_offset;
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struct r600_cmask_info cmask;
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uint64_t cmask_offset;
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uint64_t cmask_base_address_reg;
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uint32_t cmask_size;
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struct r600_resource *cmask_buffer;
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uint64_t dcc_offset; /* 0 = disabled */
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unsigned cb_color_info; /* fast clear enable bit */
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@ -3012,7 +3012,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
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/* Compute mutable surface parameters. */
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cb_color_base = tex->buffer.gpu_address >> 8;
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cb_color_fmask = 0;
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cb_color_cmask = tex->cmask.base_address_reg;
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cb_color_cmask = tex->cmask_base_address_reg;
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cb_dcc_base = 0;
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cb_color_info = cb->cb_color_info | tex->cb_color_info;
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cb_color_attrib = cb->cb_color_attrib;
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@ -82,7 +82,7 @@ bool si_prepare_for_dma_blit(struct si_context *sctx,
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* dst: If overwriting the whole texture, discard CMASK and use
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* SDMA. Otherwise, use the 3D path.
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*/
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if (dst->cmask.size && dst->dirty_level_mask & (1 << dst_level)) {
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if (dst->cmask_size && dst->dirty_level_mask & (1 << dst_level)) {
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/* The CMASK clear is only enabled for the first level. */
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assert(dst_level == 0);
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if (!util_texrange_covers_whole_level(&dst->buffer.b.b, dst_level,
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@ -94,7 +94,7 @@ bool si_prepare_for_dma_blit(struct si_context *sctx,
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}
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/* All requirements are met. Prepare textures for SDMA. */
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if (src->cmask.size && src->dirty_level_mask & (1 << src_level))
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if (src->cmask_size && src->dirty_level_mask & (1 << src_level))
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sctx->b.flush_resource(&sctx->b, &src->buffer.b.b);
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assert(!(src->dirty_level_mask & (1 << src_level)));
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@ -420,14 +420,14 @@ void si_eliminate_fast_color_clear(struct si_context *sctx,
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void si_texture_discard_cmask(struct si_screen *sscreen,
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struct si_texture *tex)
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{
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if (!tex->cmask.size)
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if (!tex->cmask_size)
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return;
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assert(tex->buffer.b.b.nr_samples <= 1);
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/* Disable CMASK. */
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memset(&tex->cmask, 0, sizeof(tex->cmask));
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tex->cmask.base_address_reg = tex->buffer.gpu_address >> 8;
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tex->cmask_size = 0;
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tex->cmask_base_address_reg = tex->buffer.gpu_address >> 8;
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tex->dirty_level_mask = 0;
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tex->cb_color_info &= ~S_028C70_FAST_CLEAR(1);
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@ -571,7 +571,9 @@ static void si_reallocate_texture_inplace(struct si_context *sctx,
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new_tex->flushed_depth_texture);
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tex->fmask_offset = new_tex->fmask_offset;
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tex->cmask = new_tex->cmask;
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tex->cmask_offset = new_tex->cmask_offset;
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tex->cmask_size = new_tex->cmask_size;
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tex->cmask_base_address_reg = new_tex->cmask_base_address_reg;
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r600_resource_reference(&tex->cmask_buffer, new_tex->cmask_buffer);
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tex->dcc_offset = new_tex->dcc_offset;
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tex->cb_color_info = new_tex->cb_color_info;
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@ -602,7 +604,7 @@ static void si_reallocate_texture_inplace(struct si_context *sctx,
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if (new_bind_flag == PIPE_BIND_LINEAR) {
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assert(!tex->htile_offset);
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assert(!tex->cmask.size);
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assert(!tex->cmask_size);
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assert(!tex->surface.fmask_size);
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assert(!tex->dcc_offset);
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assert(!tex->is_depth);
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@ -761,7 +763,7 @@ static boolean si_texture_get_handle(struct pipe_screen* screen,
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}
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if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
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(tex->cmask.size || tex->dcc_offset)) {
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(tex->cmask_size || tex->dcc_offset)) {
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/* Eliminate fast clear (both CMASK and DCC) */
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si_eliminate_fast_color_clear(sctx, tex);
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/* eliminate_fast_color_clear flushes the context */
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@ -770,7 +772,7 @@ static boolean si_texture_get_handle(struct pipe_screen* screen,
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/* Disable CMASK if flush_resource isn't going
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* to be called.
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*/
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if (tex->cmask.size)
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if (tex->cmask_size)
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si_texture_discard_cmask(sscreen, tex);
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}
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@ -984,10 +986,10 @@ void si_print_texture_info(struct si_screen *sscreen,
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tex->surface.u.gfx9.fmask.epitch);
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}
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if (tex->cmask.size) {
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if (tex->cmask_size) {
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u_log_printf(log, " CMask: offset=%"PRIu64", size=%u, "
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"alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
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tex->cmask.offset,
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tex->cmask_offset,
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tex->surface.cmask_size,
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tex->surface.cmask_alignment,
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tex->surface.u.gfx9.cmask.rb_aligned,
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@ -1038,10 +1040,10 @@ void si_print_texture_info(struct si_screen *sscreen,
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tex->surface.u.legacy.fmask.slice_tile_max,
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tex->surface.u.legacy.fmask.tiling_index);
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if (tex->cmask.size)
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if (tex->cmask_size)
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u_log_printf(log, " CMask: offset=%"PRIu64", size=%u, alignment=%u, "
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"slice_tile_max=%u\n",
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tex->cmask.offset, tex->cmask.size, tex->surface.cmask_alignment,
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tex->cmask_offset, tex->cmask_size, tex->surface.cmask_alignment,
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tex->surface.u.legacy.cmask_slice_tile_max);
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if (tex->htile_offset)
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@ -1183,13 +1185,13 @@ si_texture_create_object(struct pipe_screen *screen,
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tex->size = tex->fmask_offset + tex->surface.fmask_size;
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/* Allocate CMASK. */
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tex->cmask.size = tex->surface.cmask_size;
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tex->cmask.offset = align64(tex->size, tex->surface.cmask_alignment);
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tex->size = tex->cmask.offset + tex->cmask.size;
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tex->cmask_size = tex->surface.cmask_size;
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tex->cmask_offset = align64(tex->size, tex->surface.cmask_alignment);
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tex->size = tex->cmask_offset + tex->cmask_size;
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tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
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tex->cmask_buffer = &tex->buffer;
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if (!tex->surface.fmask_size || !tex->cmask.size) {
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if (!tex->surface.fmask_size || !tex->cmask_size) {
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FREE(tex);
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return NULL;
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}
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@ -1229,10 +1231,10 @@ si_texture_create_object(struct pipe_screen *screen,
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resource->gart_usage = buf->size;
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}
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if (tex->cmask.size) {
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if (tex->cmask_size) {
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/* Initialize the cmask to 0xCC (= compressed state). */
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si_screen_clear_buffer(sscreen, &tex->cmask_buffer->b.b,
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tex->cmask.offset, tex->cmask.size,
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tex->cmask_offset, tex->cmask_size,
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0xCCCCCCCC);
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}
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if (tex->htile_offset) {
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@ -1256,8 +1258,8 @@ si_texture_create_object(struct pipe_screen *screen,
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}
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/* Initialize the CMASK base register value. */
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tex->cmask.base_address_reg =
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(tex->buffer.gpu_address + tex->cmask.offset) >> 8;
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tex->cmask_base_address_reg =
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(tex->buffer.gpu_address + tex->cmask_offset) >> 8;
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if (sscreen->debug_flags & DBG(VM)) {
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fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
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@ -1622,8 +1624,8 @@ static void si_texture_invalidate_storage(struct si_context *sctx,
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si_alloc_resource(sscreen, &tex->buffer);
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/* Initialize the CMASK base address (needed even without CMASK). */
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tex->cmask.base_address_reg =
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(tex->buffer.gpu_address + tex->cmask.offset) >> 8;
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tex->cmask_base_address_reg =
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(tex->buffer.gpu_address + tex->cmask_offset) >> 8;
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p_atomic_inc(&sscreen->dirty_tex_counter);
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