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pan/midgard: Fix vertex texturing on early Midgard 

We use a different set of texture registers, probably to save hardware.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Andre Heider <a.heider@gmail.com>
This commit is contained in:
Alyssa Rosenzweig 2019-11-11 08:15:46 -05:00
parent 3866d0776f
commit 29f5b00e6e
1 changed files with 10 additions and 0 deletions
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10
src/panfrost/midgard/midgard_ra.c
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@ -441,6 +441,16 @@ allocate_registers(compiler_context *ctx, bool *spilled)
lcra_set_disjoint_class(l, REG_CLASS_TEXR, REG_CLASS_TEXW);
/* To save space on T720, we don't have real texture registers.
* Instead, tex inputs reuse the load/store pipeline registers, and
* tex outputs use work r0/r1. Note we still use TEXR/TEXW classes,
* noting that this handles interferences and sizes correctly. */
if (ctx->gpu_id == 0x0720) {
l->class_start[REG_CLASS_TEXR] = l->class_start[REG_CLASS_LDST];
l->class_start[REG_CLASS_TEXW] = l->class_start[REG_CLASS_WORK];
}
unsigned *found_class = calloc(sizeof(unsigned), ctx->temp_count);
mir_foreach_instr_global(ctx, ins) {