freedreno/ir3: Set up outputs for multi-slot varyings.
Necessary to avoid compiler assertion failures in: dEQP-GLES31.functional.program_interface_query.program_output.type.interface_blocks.out.named_block_explicit_location.struct.mat3x2 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
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@ -3130,7 +3130,8 @@ static void
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setup_output(struct ir3_context *ctx, nir_variable *out)
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{
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struct ir3_shader_variant *so = ctx->so;
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unsigned ncomp = glsl_get_components(out->type);
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unsigned slots = glsl_count_vec4_slots(out->type, false, false);
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unsigned ncomp = glsl_get_components(glsl_without_array(out->type));
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unsigned n = out->data.driver_location;
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unsigned frac = out->data.location_frac;
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unsigned slot = out->data.location;
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@ -3192,30 +3193,34 @@ setup_output(struct ir3_context *ctx, nir_variable *out)
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ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
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}
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compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
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so->outputs[n].slot = slot;
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so->outputs_count = MAX2(so->outputs_count, n + 1);
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so->outputs_count = out->data.driver_location + slots;
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compile_assert(ctx, so->outputs_count < ARRAY_SIZE(so->outputs));
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for (int i = 0; i < ncomp; i++) {
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unsigned idx = (n * 4) + i + frac;
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compile_assert(ctx, idx < ctx->noutputs);
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ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
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}
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for (int i = 0; i < slots; i++) {
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int slot_base = n + i;
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so->outputs[slot_base].slot = slot + i;
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/* if varying packing doesn't happen, we could end up in a situation
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* with "holes" in the output, and since the per-generation code that
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* sets up varying linkage registers doesn't expect to have more than
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* one varying per vec4 slot, pad the holes.
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*
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* Note that this should probably generate a performance warning of
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* some sort.
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*/
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for (int i = 0; i < frac; i++) {
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unsigned idx = (n * 4) + i;
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if (!ctx->outputs[idx]) {
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for (int i = 0; i < ncomp; i++) {
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unsigned idx = (slot_base * 4) + i + frac;
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compile_assert(ctx, idx < ctx->noutputs);
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ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
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}
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/* if varying packing doesn't happen, we could end up in a situation
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* with "holes" in the output, and since the per-generation code that
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* sets up varying linkage registers doesn't expect to have more than
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* one varying per vec4 slot, pad the holes.
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*
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* Note that this should probably generate a performance warning of
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* some sort.
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*/
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for (int i = 0; i < frac; i++) {
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unsigned idx = (slot_base * 4) + i;
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if (!ctx->outputs[idx]) {
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ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
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}
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}
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}
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}
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