intel/compiler: extract brw_nir_load_global_const out of rt code
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13661>
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@ -1535,3 +1535,49 @@ brw_nir_create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compile
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return nir;
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}
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nir_ssa_def *
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brw_nir_load_global_const(nir_builder *b, nir_intrinsic_instr *load_uniform,
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nir_ssa_def *base_addr, unsigned off)
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{
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assert(load_uniform->intrinsic == nir_intrinsic_load_uniform);
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assert(load_uniform->dest.is_ssa);
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assert(load_uniform->src[0].is_ssa);
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unsigned bit_size = load_uniform->dest.ssa.bit_size;
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assert(bit_size >= 8 && bit_size % 8 == 0);
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unsigned byte_size = bit_size / 8;
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nir_ssa_def *sysval;
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if (nir_src_is_const(load_uniform->src[0])) {
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uint64_t offset = off +
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nir_intrinsic_base(load_uniform) +
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nir_src_as_uint(load_uniform->src[0]);
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/* Things should be component-aligned. */
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assert(offset % byte_size == 0);
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unsigned suboffset = offset % 64;
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uint64_t aligned_offset = offset - suboffset;
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/* Load two just in case we go over a 64B boundary */
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nir_ssa_def *data[2];
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for (unsigned i = 0; i < 2; i++) {
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nir_ssa_def *addr = nir_iadd_imm(b, base_addr, aligned_offset + i * 64);
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data[i] = nir_load_global_const_block_intel(b, 16, addr,
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nir_imm_true(b));
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}
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sysval = nir_extract_bits(b, data, 2, suboffset * 8,
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load_uniform->num_components, bit_size);
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} else {
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nir_ssa_def *offset32 =
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nir_iadd_imm(b, load_uniform->src[0].ssa,
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off + nir_intrinsic_base(load_uniform));
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nir_ssa_def *addr = nir_iadd(b, base_addr, nir_u2u64(b, offset32));
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sysval = nir_load_global_constant(b, addr, byte_size,
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load_uniform->num_components, bit_size);
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}
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return sysval;
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}
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@ -27,6 +27,7 @@
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#include "brw_reg.h"
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#include "compiler/nir/nir.h"
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#include "brw_compiler.h"
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#include "nir_builder.h"
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#ifdef __cplusplus
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extern "C" {
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@ -191,6 +192,10 @@ nir_shader *brw_nir_create_passthrough_tcs(void *mem_ctx,
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bool brw_nir_move_interpolation_to_top(nir_shader *nir);
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bool brw_nir_demote_sample_qualifiers(nir_shader *nir);
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nir_ssa_def *brw_nir_load_global_const(nir_builder *b,
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nir_intrinsic_instr *load_uniform,
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nir_ssa_def *base_addr,
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unsigned off);
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#ifdef __cplusplus
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}
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@ -140,47 +140,10 @@ lower_rt_intrinsics_impl(nir_function_impl *impl,
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if (stage == MESA_SHADER_COMPUTE)
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break;
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assert(intrin->dest.is_ssa);
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assert(intrin->src[0].is_ssa);
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sysval = brw_nir_load_global_const(b, intrin,
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nir_load_btd_global_arg_addr_intel(b),
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BRW_RT_PUSH_CONST_OFFSET);
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unsigned bit_size = intrin->dest.ssa.bit_size;
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assert(bit_size >= 8 && bit_size % 8 == 0);
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unsigned byte_size = bit_size / 8;
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if (nir_src_is_const(intrin->src[0])) {
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uint64_t offset = BRW_RT_PUSH_CONST_OFFSET +
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nir_intrinsic_base(intrin) +
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nir_src_as_uint(intrin->src[0]);
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/* Things should be component-aligned. */
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assert(offset % byte_size == 0);
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unsigned suboffset = offset % 64;
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uint64_t aligned_offset = offset - suboffset;
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/* Load two just in case we go over a 64B boundary */
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nir_ssa_def *data[2];
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for (unsigned i = 0; i < 2; i++) {
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nir_ssa_def *addr =
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nir_iadd_imm(b, nir_load_btd_global_arg_addr_intel(b),
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aligned_offset + i * 64);
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data[i] = nir_load_global_const_block_intel(b, 16, addr,
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nir_imm_true(b));
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}
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sysval = nir_extract_bits(b, data, 2, suboffset * 8,
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intrin->num_components, bit_size);
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} else {
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nir_ssa_def *offset32 =
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nir_iadd_imm(b, intrin->src[0].ssa,
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BRW_RT_PUSH_CONST_OFFSET +
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nir_intrinsic_base(intrin));
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nir_ssa_def *addr =
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nir_iadd(b, nir_load_btd_global_arg_addr_intel(b),
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nir_u2u64(b, offset32));
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sysval = nir_load_global_constant(b, addr, byte_size,
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intrin->num_components, bit_size);
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}
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break;
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}
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