radeonsi: fix fractional odd tessellation spacing for Polaris
ported from Vulkan (and no source explains why this is needed) Cc: 12.0 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@ -240,6 +240,7 @@ void si_begin_new_cs(struct si_context *ctx)
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ctx->last_ls_hs_config = -1;
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ctx->last_ls_hs_config = -1;
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ctx->last_rast_prim = -1;
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ctx->last_rast_prim = -1;
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ctx->last_sc_line_stipple = ~0;
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ctx->last_sc_line_stipple = ~0;
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ctx->last_vtx_reuse_depth = -1;
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ctx->emit_scratch_reloc = true;
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ctx->emit_scratch_reloc = true;
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ctx->last_ls = NULL;
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ctx->last_ls = NULL;
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ctx->last_tcs = NULL;
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ctx->last_tcs = NULL;
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@ -303,6 +303,7 @@ struct si_context {
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int last_ls_hs_config;
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int last_ls_hs_config;
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int last_rast_prim;
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int last_rast_prim;
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unsigned last_sc_line_stipple;
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unsigned last_sc_line_stipple;
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int last_vtx_reuse_depth;
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int current_rast_prim; /* primitive type after TES, GS */
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int current_rast_prim; /* primitive type after TES, GS */
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unsigned last_gsvs_itemsize;
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unsigned last_gsvs_itemsize;
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@ -3866,7 +3866,8 @@ static void si_init_config(struct si_context *sctx)
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si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
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si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
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S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
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S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
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S_028424_OVERWRITE_COMBINER_WATERMARK(4));
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S_028424_OVERWRITE_COMBINER_WATERMARK(4));
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si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
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if (sctx->b.family < CHIP_POLARIS10)
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si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
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si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
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si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
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vgt_tess_distribution =
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vgt_tess_distribution =
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@ -438,6 +438,25 @@ static void si_emit_draw_registers(struct si_context *sctx,
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unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
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unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
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unsigned ia_multi_vgt_param, ls_hs_config, num_patches = 0;
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unsigned ia_multi_vgt_param, ls_hs_config, num_patches = 0;
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/* Polaris needs different VTX_REUSE_DEPTH settings depending on
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* whether the "fractional odd" tessellation spacing is used.
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*/
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if (sctx->b.family >= CHIP_POLARIS10) {
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struct si_shader_selector *tes = sctx->tes_shader.cso;
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unsigned vtx_reuse_depth = 30;
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if (tes &&
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tes->info.properties[TGSI_PROPERTY_TES_SPACING] ==
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PIPE_TESS_SPACING_FRACTIONAL_ODD)
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vtx_reuse_depth = 14;
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if (vtx_reuse_depth != sctx->last_vtx_reuse_depth) {
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radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
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vtx_reuse_depth);
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sctx->last_vtx_reuse_depth = vtx_reuse_depth;
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}
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}
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if (sctx->tes_shader.cso)
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if (sctx->tes_shader.cso)
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si_emit_derived_tess_state(sctx, info, &num_patches);
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si_emit_derived_tess_state(sctx, info, &num_patches);
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