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freedreno/registers: update dsi registers to support dsc 

Display Stream compression (DSC) compresses the display stream in
host which is later decoded by panel. This requires addition of 3 new
DSI registers to support DSC over DSI.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14967>
This commit is contained in:
Vinod Koul 2022-04-01 16:53:04 +05:30 committed by Marge Bot
parent b672814fe5
commit 28ae397be1
1 changed files with 22 additions and 0 deletions
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22
src/freedreno/registers/dsi/dsi.xml
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@ -361,6 +361,28 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<bitfield name="MAJOR" low="24" high="31" type="uint"/>
</reg32>
<reg32 offset="0x002d4" name="CPHY_MODE_CTRL"/>
<reg32 offset="0x0029c" name="VIDEO_COMPRESSION_MODE_CTRL">
<bitfield name="WC" low="16" high="31" type="uint"/>
<bitfield name="DATATYPE" low="8" high="13" type="uint"/>
<bitfield name="PKT_PER_LINE" low="6" high="7" type="uint"/>
<bitfield name="EOL_BYTE_NUM" low="4" high="5" type="uint"/>
<bitfield name="EN" pos="0" type="boolean"/>
</reg32>
<reg32 offset="0x002a4" name="COMMAND_COMPRESSION_MODE_CTRL">
<bitfield name="STREAM1_DATATYPE" low="24" high="29" type="uint"/>
<bitfield name="STREAM1_PKT_PER_LINE" low="22" high="23" type="uint"/>
<bitfield name="STREAM1_EOL_BYTE_NUM" low="20" high="21" type="uint"/>
<bitfield name="STREAM1_EN" pos="16" type="boolean"/>
<bitfield name="STREAM0_DATATYPE" low="8" high="13" type="uint"/>
<bitfield name="STREAM0_PKT_PER_LINE" low="6" high="7" type="uint"/>
<bitfield name="STREAM0_EOL_BYTE_NUM" low="4" high="5" type="uint"/>
<bitfield name="STREAM0_EN" pos="0" type="boolean"/>
</reg32>
<reg32 offset="0x002a8" name="COMMAND_COMPRESSION_MODE_CTRL2">
<bitfield name="STREAM1_SLICE_WIDTH" low="16" high="31" type="uint"/>
<bitfield name="STREAM0_SLICE_WIDTH" low="0" high="15" type="uint"/>
</reg32>
</domain>
</database>