r600g: only do depth-only or stencil-only in-place decompression
instead of always doing both. Usually, only depth is needed, so stencil decompression is useless. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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c23c92c965
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27b102e7fd
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@ -783,6 +783,12 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx,
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va = tmp->resource.gpu_address;
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if (state->format == PIPE_FORMAT_X24S8_UINT ||
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state->format == PIPE_FORMAT_S8X24_UINT ||
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state->format == PIPE_FORMAT_X32_S8X24_UINT ||
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state->format == PIPE_FORMAT_S8_UINT)
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view->is_stencil_sampler = true;
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view->tex_resource = &tmp->resource;
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view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
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S_030000_PITCH((pitch / 8) - 1) |
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@ -1823,9 +1829,9 @@ static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_
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S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
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S_028000_COPY_CENTROID(1) |
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S_028000_COPY_SAMPLE(a->copy_sample);
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} else if (a->flush_depthstencil_in_place) {
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db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(1) |
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S_028000_STENCIL_COMPRESS_DISABLE(1);
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} else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
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db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
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S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
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db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
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}
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if (a->htile_clear) {
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@ -202,20 +202,28 @@ static void r600_blit_decompress_depth(struct pipe_context *ctx,
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static void r600_blit_decompress_depth_in_place(struct r600_context *rctx,
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struct r600_texture *texture,
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bool is_stencil_sampler,
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unsigned first_level, unsigned last_level,
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unsigned first_layer, unsigned last_layer)
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{
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struct pipe_surface *zsurf, surf_tmpl = {{0}};
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unsigned layer, max_layer, checked_last_layer, level;
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unsigned *dirty_level_mask;
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/* Enable decompression in DB_RENDER_CONTROL */
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rctx->db_misc_state.flush_depthstencil_in_place = true;
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if (is_stencil_sampler) {
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rctx->db_misc_state.flush_stencil_inplace = true;
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dirty_level_mask = &texture->stencil_dirty_level_mask;
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} else {
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rctx->db_misc_state.flush_depth_inplace = true;
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dirty_level_mask = &texture->dirty_level_mask;
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}
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r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
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surf_tmpl.format = texture->resource.b.b.format;
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for (level = first_level; level <= last_level; level++) {
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if (!(texture->dirty_level_mask & (1 << level)))
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if (!(*dirty_level_mask & (1 << level)))
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continue;
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surf_tmpl.u.tex.level = level;
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@ -242,12 +250,13 @@ static void r600_blit_decompress_depth_in_place(struct r600_context *rctx,
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/* The texture will always be dirty if some layers or samples aren't flushed.
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* I don't think this case occurs often though. */
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if (first_layer == 0 && last_layer == max_layer) {
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texture->dirty_level_mask &= ~(1 << level);
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*dirty_level_mask &= ~(1 << level);
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}
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}
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/* Disable decompression in DB_RENDER_CONTROL */
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rctx->db_misc_state.flush_depthstencil_in_place = false;
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rctx->db_misc_state.flush_depth_inplace = false;
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rctx->db_misc_state.flush_stencil_inplace = false;
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r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
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}
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@ -259,12 +268,14 @@ void r600_decompress_depth_textures(struct r600_context *rctx,
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while (depth_texture_mask) {
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struct pipe_sampler_view *view;
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struct r600_pipe_sampler_view *rview;
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struct r600_texture *tex;
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i = u_bit_scan(&depth_texture_mask);
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view = &textures->views[i]->base;
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assert(view);
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rview = (struct r600_pipe_sampler_view*)view;
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tex = (struct r600_texture *)view->texture;
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assert(tex->is_depth && !tex->is_flushing_texture);
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@ -272,6 +283,7 @@ void r600_decompress_depth_textures(struct r600_context *rctx,
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if (rctx->b.chip_class >= EVERGREEN ||
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r600_can_read_depth(tex)) {
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r600_blit_decompress_depth_in_place(rctx, tex,
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rview->is_stencil_sampler,
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view->u.tex.first_level, view->u.tex.last_level,
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0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
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} else {
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@ -367,9 +379,14 @@ static bool r600_decompress_subresource(struct pipe_context *ctx,
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if (rtex->is_depth && !rtex->is_flushing_texture) {
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if (rctx->b.chip_class >= EVERGREEN ||
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r600_can_read_depth(rtex)) {
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r600_blit_decompress_depth_in_place(rctx, rtex,
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r600_blit_decompress_depth_in_place(rctx, rtex, false,
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level, level,
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first_layer, last_layer);
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if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
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r600_blit_decompress_depth_in_place(rctx, rtex, true,
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level, level,
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first_layer, last_layer);
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}
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} else {
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if (!r600_init_flushed_depth_texture(ctx, tex, NULL))
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return false; /* error */
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@ -109,7 +109,8 @@ struct r600_db_misc_state {
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struct r600_atom atom;
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bool occlusion_query_enabled;
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bool flush_depthstencil_through_cb;
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bool flush_depthstencil_in_place;
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bool flush_depth_inplace;
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bool flush_stencil_inplace;
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bool copy_depth, copy_stencil;
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unsigned copy_sample;
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unsigned log_samples;
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@ -253,6 +254,7 @@ struct r600_pipe_sampler_view {
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struct r600_resource *tex_resource;
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uint32_t tex_resource_words[8];
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bool skip_mip_address_reloc;
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bool is_stencil_sampler;
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};
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struct r600_rasterizer_state {
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@ -710,6 +710,12 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
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break;
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}
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if (state->format == PIPE_FORMAT_X24S8_UINT ||
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state->format == PIPE_FORMAT_S8X24_UINT ||
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state->format == PIPE_FORMAT_X32_S8X24_UINT ||
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state->format == PIPE_FORMAT_S8_UINT)
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view->is_stencil_sampler = true;
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view->tex_resource = &tmp->resource;
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view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
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S_038000_TILE_MODE(array_mode) |
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@ -1659,9 +1665,9 @@ static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom
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if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
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rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
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db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
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} else if (a->flush_depthstencil_in_place) {
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db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(1) |
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S_028D0C_STENCIL_COMPRESS_DISABLE(1);
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} else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
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db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
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S_028D0C_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
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db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
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}
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if (a->htile_clear) {
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