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anv/genxml/intel/fs: fix binding shader record entry 

Bit is flipped compared to all the other packets.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 705395344d ("intel/fs: Add support for compiling bindless shaders with resume shaders")
Fixes: c3ac9afca3 ("anv: Create and return ray-tracing pipeline SBT handles")
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15078>
This commit is contained in:
Lionel Landwerlin 2022-01-31 12:43:04 +00:00 committed by Marge Bot
parent 5f3e50b27c
commit 2763a8af5a
3 changed files with 5 additions and 4 deletions
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2
src/intel/compiler/brw_fs.cpp
View File

@ -10328,7 +10328,7 @@ brw_bsr(const struct intel_device_info *devinfo,
assert(local_arg_offset % 8 == 0);
return offset |
SET_BITS(simd_size > 8, 4, 4) |
SET_BITS(simd_size == 8, 4, 4) |
SET_BITS(local_arg_offset / 8, 2, 0);
}

4
src/intel/genxml/gen_rt.xml
View File

@ -3,8 +3,8 @@
<struct name="BINDLESS_SHADER_RECORD" length="2">
<field name="Offset To Local Arguments" start="0" end="2" type="uint"/>
<field name="Bindless Shader Dispatch Mode" start="4" end="4" type="uint">
<value name="SIMD8" value="0"/>
<value name="SIMD16" value="1"/>
<value name="RT_SIMD16" value="0"/>
<value name="RT_SIMD8" value="1"/>
</field>
<field name="Kernel Start Pointer" start="6" end="31" type="offset"/>
</struct>

3
src/intel/vulkan/anv_private.h
View File

@ -3442,7 +3442,8 @@ anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
\
(struct GFX_BINDLESS_SHADER_RECORD) { \
.OffsetToLocalArguments = (local_arg_offset) / 8, \
.BindlessShaderDispatchMode = prog_data->simd_size / 16, \
.BindlessShaderDispatchMode = \
prog_data->simd_size == 16 ? RT_SIMD16 : RT_SIMD8, \
.KernelStartPointer = bin->kernel.offset, \
}; \
})