anv/nir: Unify inputs_read/outputs_written between geometry stages
inputs_read/outputs_written are used for a shader stage to determine the layout of input and output storage. Adjacent stages must agree on the layout, so adjacent input/output bitfields must match. Most of the time, cross-stage optimizations make that happen anyway, but there are some cases (with special values like clip distances and point size) where this doesn't happen. Fixes crashes in dEQP-VK.subgroups.*.framebuffer.*_tess_eval Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3210 Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6102>
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@ -1505,14 +1505,39 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
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void *stage_ctx = ralloc_context(NULL);
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anv_pipeline_lower_nir(&pipeline->base, stage_ctx, &stages[s], layout);
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if (prev_stage && compiler->glsl_compiler_options[s].NirOptions->unify_interfaces) {
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prev_stage->nir->info.outputs_written |= stages[s].nir->info.inputs_read &
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~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
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stages[s].nir->info.inputs_read |= prev_stage->nir->info.outputs_written &
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~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
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prev_stage->nir->info.patch_outputs_written |= stages[s].nir->info.patch_inputs_read;
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stages[s].nir->info.patch_inputs_read |= prev_stage->nir->info.patch_outputs_written;
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}
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ralloc_free(stage_ctx);
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stages[s].feedback.duration += os_time_get_nano() - stage_start;
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prev_stage = &stages[s];
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}
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prev_stage = NULL;
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for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
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if (!stages[s].entrypoint)
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continue;
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int64_t stage_start = os_time_get_nano();
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void *stage_ctx = ralloc_context(NULL);
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nir_xfb_info *xfb_info = NULL;
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if (s == MESA_SHADER_VERTEX ||
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s == MESA_SHADER_TESS_EVAL ||
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s == MESA_SHADER_GEOMETRY)
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xfb_info = nir_gather_xfb_info(stages[s].nir, stage_ctx);
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anv_pipeline_lower_nir(&pipeline->base, stage_ctx, &stages[s], layout);
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switch (s) {
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case MESA_SHADER_VERTEX:
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anv_pipeline_compile_vs(compiler, stage_ctx, pipeline,
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