aco: implement 16-bit nir_op_ftrunc/nir_op_fround_even
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
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@ -1909,10 +1909,14 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
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break;
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}
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case nir_op_ftrunc: {
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if (dst.size() == 1) {
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Temp src = get_alu_src(ctx, instr->src[0]);
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if (dst.regClass() == v2b) {
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Temp tmp = bld.vop1(aco_opcode::v_trunc_f16, bld.def(v1), src);
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bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(v2b), tmp);
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} else if (dst.regClass() == v1) {
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emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f32, dst);
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} else if (dst.size() == 2) {
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emit_trunc_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
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} else if (dst.regClass() == v2) {
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emit_trunc_f64(ctx, bld, Definition(dst), src);
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} else {
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fprintf(stderr, "Unimplemented NIR instr bit size: ");
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nir_print_instr(&instr->instr, stderr);
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@ -1921,15 +1925,17 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
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break;
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}
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case nir_op_fround_even: {
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if (dst.size() == 1) {
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Temp src0 = get_alu_src(ctx, instr->src[0]);
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if (dst.regClass() == v2b) {
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Temp tmp = bld.vop1(aco_opcode::v_rndne_f16, bld.def(v1), src0);
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bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(v2b), tmp);
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} else if (dst.regClass() == v1) {
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emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst);
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} else if (dst.size() == 2) {
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} else if (dst.regClass() == v2) {
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if (ctx->options->chip_class >= GFX7) {
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emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst);
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} else {
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/* GFX6 doesn't support V_RNDNE_F64, lower it. */
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Temp src0 = get_alu_src(ctx, instr->src[0]);
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Temp src0_lo = bld.tmp(v1), src0_hi = bld.tmp(v1);
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bld.pseudo(aco_opcode::p_split_vector, Definition(src0_lo), Definition(src0_hi), src0);
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