radeonsi/gfx9: force the micro tile mode for MSAA resolve correctly on gfx9
Fixes: 69ea473
"amd/addrlib: update to the latest version"
Closes: #2325
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
This commit is contained in:
parent
60e0db3bfb
commit
269953e779
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@ -971,6 +971,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
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/* This is only called when expecting a tiled layout. */
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/* This is only called when expecting a tiled layout. */
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static int
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static int
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gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
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gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
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struct radeon_surf *surf,
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ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
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ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
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bool is_fmask, AddrSwizzleMode *swizzle_mode)
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bool is_fmask, AddrSwizzleMode *swizzle_mode)
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{
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{
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@ -1002,6 +1003,19 @@ gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
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sin.flags.fmask = 1;
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sin.flags.fmask = 1;
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}
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}
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if (surf->flags & RADEON_SURF_FORCE_MICRO_TILE_MODE) {
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sin.forbiddenBlock.linear = 1;
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if (surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
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sin.preferredSwSet.sw_D = 1;
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else if (surf->micro_tile_mode == RADEON_MICRO_MODE_THIN)
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sin.preferredSwSet.sw_S = 1;
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else if (surf->micro_tile_mode == RADEON_MICRO_MODE_DEPTH)
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sin.preferredSwSet.sw_Z = 1;
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else if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED)
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sin.preferredSwSet.sw_R = 1;
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}
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ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
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ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
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if (ret != ADDR_OK)
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if (ret != ADDR_OK)
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return ret;
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return ret;
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@ -1314,7 +1328,7 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
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fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
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fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
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fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
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fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
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ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
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ret = gfx9_get_preferred_swizzle_mode(addrlib, surf, in,
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true, &fin.swizzleMode);
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true, &fin.swizzleMode);
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if (ret != ADDR_OK)
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if (ret != ADDR_OK)
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return ret;
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return ret;
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@ -1536,7 +1550,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
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break;
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break;
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}
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}
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r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
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r = gfx9_get_preferred_swizzle_mode(addrlib, surf, &AddrSurfInfoIn,
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false, &AddrSurfInfoIn.swizzleMode);
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false, &AddrSurfInfoIn.swizzleMode);
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if (r)
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if (r)
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return r;
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return r;
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@ -1575,7 +1589,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
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AddrSurfInfoIn.format = ADDR_FMT_8;
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AddrSurfInfoIn.format = ADDR_FMT_8;
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if (!AddrSurfInfoIn.flags.depth) {
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if (!AddrSurfInfoIn.flags.depth) {
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r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
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r = gfx9_get_preferred_swizzle_mode(addrlib, surf, &AddrSurfInfoIn,
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false, &AddrSurfInfoIn.swizzleMode);
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false, &AddrSurfInfoIn.swizzleMode);
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if (r)
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if (r)
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goto error;
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goto error;
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@ -73,6 +73,7 @@ enum radeon_micro_mode {
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#define RADEON_SURF_FORCE_SWIZZLE_MODE (1 << 28)
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#define RADEON_SURF_FORCE_SWIZZLE_MODE (1 << 28)
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#define RADEON_SURF_NO_FMASK (1 << 29)
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#define RADEON_SURF_NO_FMASK (1 << 29)
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#define RADEON_SURF_NO_HTILE (1 << 30)
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#define RADEON_SURF_NO_HTILE (1 << 30)
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#define RADEON_SURF_FORCE_MICRO_TILE_MODE (1u << 31)
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struct legacy_surf_level {
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struct legacy_surf_level {
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uint64_t offset;
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uint64_t offset;
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@ -1162,10 +1162,13 @@ resolve_to_temp:
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templ.array_size = 1;
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templ.array_size = 1;
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templ.usage = PIPE_USAGE_DEFAULT;
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templ.usage = PIPE_USAGE_DEFAULT;
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templ.flags = SI_RESOURCE_FLAG_FORCE_MSAA_TILING |
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templ.flags = SI_RESOURCE_FLAG_FORCE_MSAA_TILING |
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SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE |
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SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(src->surface.micro_tile_mode) |
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SI_RESOURCE_FLAG_DISABLE_DCC;
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SI_RESOURCE_FLAG_DISABLE_DCC;
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/* The src and dst microtile modes must be the same. */
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/* The src and dst microtile modes must be the same. */
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if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
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if (sctx->chip_class <= GFX8 &&
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src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
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templ.bind = PIPE_BIND_SCANOUT;
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templ.bind = PIPE_BIND_SCANOUT;
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else
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else
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templ.bind = 0;
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templ.bind = 0;
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@ -116,6 +116,11 @@
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#define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
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#define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
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/* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
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/* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
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#define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
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#define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
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/* Set a micro tile mode: */
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#define SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE (PIPE_RESOURCE_FLAG_DRV_PRIV << 9)
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#define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT (util_logbase2(PIPE_RESOURCE_FLAG_DRV_PRIV) + 10)
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#define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(x) (((x) & 0x3) << SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT)
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#define SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(x) (((x) >> SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT) & 0x3)
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enum si_clear_code
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enum si_clear_code
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{
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{
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@ -330,6 +330,12 @@ static int si_init_surface(struct si_screen *sscreen,
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if (sscreen->debug_flags & DBG(NO_FMASK))
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if (sscreen->debug_flags & DBG(NO_FMASK))
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flags |= RADEON_SURF_NO_FMASK;
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flags |= RADEON_SURF_NO_FMASK;
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if (sscreen->info.chip_class == GFX9 &&
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(ptex->flags & SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE)) {
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flags |= RADEON_SURF_FORCE_MICRO_TILE_MODE;
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surface->micro_tile_mode = SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(ptex->flags);
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}
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if (sscreen->info.chip_class >= GFX10 &&
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if (sscreen->info.chip_class >= GFX10 &&
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(ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING)) {
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(ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING)) {
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flags |= RADEON_SURF_FORCE_SWIZZLE_MODE;
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flags |= RADEON_SURF_FORCE_SWIZZLE_MODE;
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