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asahi: Respect mip level when rendering 

Use hardware mip level field.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903>
This commit is contained in:
Alyssa Rosenzweig 2022-02-06 09:30:36 -05:00 committed by Marge Bot
parent 1a3e21a4de
commit 266382d252
1 changed files with 6 additions and 1 deletions
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7
src/gallium/drivers/asahi/agx_state.c
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@ -722,6 +722,10 @@ agx_set_framebuffer_state(struct pipe_context *pctx,
struct agx_resource *tex = agx_resource(surf->texture);
const struct util_format_description *desc =
util_format_description(surf->format);
unsigned level = surf->u.tex.level;
assert(surf->u.tex.first_layer == 0);
assert(surf->u.tex.last_layer == 0);
agx_pack(ctx->render_target[i], RENDER_TARGET, cfg) {
cfg.layout = agx_translate_layout(tex->modifier);
@ -732,10 +736,11 @@ agx_set_framebuffer_state(struct pipe_context *pctx,
cfg.swizzle_a = agx_channel_from_pipe(desc->swizzle[3]);
cfg.width = state->width;
cfg.height = state->height;
cfg.level = surf->u.tex.level;
cfg.buffer = tex->bo->ptr.gpu;
cfg.stride = (tex->modifier == DRM_FORMAT_MOD_LINEAR) ?
(tex->slices[0].line_stride - 4) :
(tex->slices[level].line_stride - 4) :
AGX_RT_STRIDE_TILED;
};
}