asahi: Respect mip level when rendering
Use hardware mip level field. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903>
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@ -722,6 +722,10 @@ agx_set_framebuffer_state(struct pipe_context *pctx,
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struct agx_resource *tex = agx_resource(surf->texture);
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struct agx_resource *tex = agx_resource(surf->texture);
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const struct util_format_description *desc =
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const struct util_format_description *desc =
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util_format_description(surf->format);
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util_format_description(surf->format);
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unsigned level = surf->u.tex.level;
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assert(surf->u.tex.first_layer == 0);
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assert(surf->u.tex.last_layer == 0);
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agx_pack(ctx->render_target[i], RENDER_TARGET, cfg) {
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agx_pack(ctx->render_target[i], RENDER_TARGET, cfg) {
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cfg.layout = agx_translate_layout(tex->modifier);
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cfg.layout = agx_translate_layout(tex->modifier);
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@ -732,10 +736,11 @@ agx_set_framebuffer_state(struct pipe_context *pctx,
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cfg.swizzle_a = agx_channel_from_pipe(desc->swizzle[3]);
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cfg.swizzle_a = agx_channel_from_pipe(desc->swizzle[3]);
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cfg.width = state->width;
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cfg.width = state->width;
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cfg.height = state->height;
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cfg.height = state->height;
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cfg.level = surf->u.tex.level;
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cfg.buffer = tex->bo->ptr.gpu;
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cfg.buffer = tex->bo->ptr.gpu;
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cfg.stride = (tex->modifier == DRM_FORMAT_MOD_LINEAR) ?
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cfg.stride = (tex->modifier == DRM_FORMAT_MOD_LINEAR) ?
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(tex->slices[0].line_stride - 4) :
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(tex->slices[level].line_stride - 4) :
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AGX_RT_STRIDE_TILED;
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AGX_RT_STRIDE_TILED;
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};
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};
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}
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}
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