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intel/compiler: Add new variant for TXF_CMS_W 

This allows, for example, fs_inst::components_read() without passing
devinfo as extra argument.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>
This commit is contained in:
Topi Pohjolainen 2020-07-07 23:54:00 -07:00 committed by Sagar Ghuge
parent 24831bbd40
commit 261dd6c8f8
4 changed files with 20 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/intel/compiler/brw_eu_defines.h
View File

@ -356,6 +356,7 @@ enum opcode {
SHADER_OPCODE_TXF_CMS_LOGICAL,
SHADER_OPCODE_TXF_CMS_W,
SHADER_OPCODE_TXF_CMS_W_LOGICAL,
SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL,
SHADER_OPCODE_TXF_UMS,
SHADER_OPCODE_TXF_UMS_LOGICAL,
SHADER_OPCODE_TXF_MCS,

19
src/intel/compiler/brw_fs.cpp
View File

@ -778,6 +778,7 @@ fs_inst::components_read(unsigned i) const
case FS_OPCODE_TXB_LOGICAL:
case SHADER_OPCODE_TXF_CMS_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
case SHADER_OPCODE_TXF_UMS_LOGICAL:
case SHADER_OPCODE_TXF_MCS_LOGICAL:
case SHADER_OPCODE_LOD_LOGICAL:
@ -797,9 +798,14 @@ fs_inst::components_read(unsigned i) const
else if (i == TEX_LOGICAL_SRC_TG4_OFFSET)
return 2;
/* MCS */
else if (i == TEX_LOGICAL_SRC_MCS && opcode == SHADER_OPCODE_TXF_CMS_W_LOGICAL)
return 2;
else
else if (i == TEX_LOGICAL_SRC_MCS) {
if (opcode == SHADER_OPCODE_TXF_CMS_W_LOGICAL)
return 2;
else if (opcode == SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL)
return 4;
else
return 1;
} else
return 1;
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
@ -7000,6 +7006,7 @@ fs_visitor::lower_logical_sends()
break;
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_CMS_W);
break;
@ -7632,6 +7639,12 @@ get_lowered_simd_width(const struct intel_device_info *devinfo,
case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
return get_sampler_lowered_simd_width(devinfo, inst);
/* On gfx12 parameters are fixed to 16-bit values and therefore they all
* always fit regardless of the execution size.
*/
case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
return MIN2(16, inst->exec_size);
case SHADER_OPCODE_TXD_LOGICAL:
/* TXD is unsupported in SIMD16 mode. */
return 8;

1
src/intel/compiler/brw_fs_copy_propagation.cpp
View File

@ -901,6 +901,7 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
case FS_OPCODE_TXB_LOGICAL:
case SHADER_OPCODE_TXF_CMS_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
case SHADER_OPCODE_TXF_UMS_LOGICAL:
case SHADER_OPCODE_TXF_MCS_LOGICAL:
case SHADER_OPCODE_LOD_LOGICAL:

2
src/intel/compiler/brw_shader.cpp
View File

@ -257,6 +257,8 @@ brw_instruction_name(const struct intel_device_info *devinfo, enum opcode op)
return "txf_cms_w";
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
return "txf_cms_w_logical";
case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
return "txf_cms_w_gfx12_logical";
case SHADER_OPCODE_TXF_UMS:
return "txf_ums";
case SHADER_OPCODE_TXF_UMS_LOGICAL: