radeonsi: pin the winsys thread to the requested L3 cache (v2)
v2: rebase Reviewed-by: Brian Paul <brianp@vmware.com>
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8016639f63
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25ffb84016
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@ -257,6 +257,14 @@ struct radeon_winsys {
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void (*query_info)(struct radeon_winsys *ws,
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struct radeon_info *info);
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/**
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* A hint for the winsys that it should pin its execution threads to
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* a group of cores sharing a specific L3 cache if the CPU has multiple
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* L3 caches. This is needed for good multithreading performance on
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* AMD Zen CPUs.
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*/
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void (*pin_threads_to_L3_cache)(struct radeon_winsys *ws, unsigned cache);
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/**************************************************************************
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* Buffer management. Buffer attributes are mostly fixed over its lifetime.
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*
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@ -346,6 +346,20 @@ static void si_set_log_context(struct pipe_context *ctx,
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u_log_add_auto_logger(log, si_auto_log_cs, sctx);
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}
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static void si_set_context_param(struct pipe_context *ctx,
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enum pipe_context_param param,
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unsigned value)
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{
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struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
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switch (param) {
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case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
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ws->pin_threads_to_L3_cache(ws, value);
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break;
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default:;
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}
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}
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static struct pipe_context *si_create_context(struct pipe_screen *screen,
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unsigned flags)
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{
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@ -366,6 +380,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
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sctx->b.emit_string_marker = si_emit_string_marker;
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sctx->b.set_debug_callback = si_set_debug_callback;
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sctx->b.set_log_context = si_set_log_context;
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sctx->b.set_context_param = si_set_context_param;
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sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
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sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
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@ -30,6 +30,7 @@
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#include "amdgpu_cs.h"
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#include "amdgpu_public.h"
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#include "util/u_cpu_detect.h"
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#include "util/u_hash_table.h"
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#include "util/hash_table.h"
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#include "util/xmlconfig.h"
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@ -235,6 +236,14 @@ static const char* amdgpu_get_chip_name(struct radeon_winsys *ws)
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return amdgpu_get_marketing_name(dev);
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}
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static void amdgpu_pin_threads_to_L3_cache(struct radeon_winsys *rws,
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unsigned cache)
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{
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struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
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util_pin_thread_to_L3(ws->cs_queue.threads[0], cache,
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util_cpu_caps.cores_per_L3);
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}
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PUBLIC struct radeon_winsys *
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amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
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@ -314,6 +323,7 @@ amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
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ws->base.query_value = amdgpu_query_value;
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ws->base.read_registers = amdgpu_read_registers;
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ws->base.get_chip_name = amdgpu_get_chip_name;
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ws->base.pin_threads_to_L3_cache = amdgpu_pin_threads_to_L3_cache;
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amdgpu_bo_init_functions(ws);
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amdgpu_cs_init_functions(ws);
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@ -29,6 +29,7 @@
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#include "radeon_drm_cs.h"
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#include "radeon_drm_public.h"
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#include "util/u_cpu_detect.h"
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#include "util/u_memory.h"
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#include "util/u_hash_table.h"
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@ -797,6 +798,17 @@ static int handle_compare(void *key1, void *key2)
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return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
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}
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static void radeon_pin_threads_to_L3_cache(struct radeon_winsys *ws,
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unsigned cache)
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{
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struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
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if (util_queue_is_initialized(&rws->cs_queue)) {
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util_pin_thread_to_L3(rws->cs_queue.threads[0], cache,
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util_cpu_caps.cores_per_L3);
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}
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}
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PUBLIC struct radeon_winsys *
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radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config,
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radeon_screen_create_t screen_create)
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@ -864,6 +876,7 @@ radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config,
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ws->base.unref = radeon_winsys_unref;
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ws->base.destroy = radeon_winsys_destroy;
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ws->base.query_info = radeon_query_info;
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ws->base.pin_threads_to_L3_cache = radeon_pin_threads_to_L3_cache;
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ws->base.cs_request_feature = radeon_cs_request_feature;
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ws->base.query_value = radeon_query_value;
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ws->base.read_registers = radeon_read_registers;
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