freedreno/a6xx: Don't set unknown bit when tiling differs
There is a bit here that's sometimes set, but it's generally not related to whether tiling differs between src and dst. Let's stop setting it until we know more. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5717>
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@ -496,7 +496,6 @@ emit_blit_or_clear_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
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const struct pipe_box *dbox = &info->dst.box;
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struct fd_resource *dst;
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enum a6xx_format sfmt, dfmt;
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enum a6xx_tile_mode stile, dtile;
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int sx1, sy1, sx2, sy2;
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int dx1, dy1, dx2, dy2;
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@ -515,9 +514,6 @@ emit_blit_or_clear_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
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sfmt = fd6_pipe2color(info->src.format);
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dfmt = fd6_pipe2color(info->dst.format);
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stile = fd_resource_tile_mode(info->src.resource, info->src.level);
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dtile = fd_resource_tile_mode(info->dst.resource, info->dst.level);
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uint32_t nr_samples = fd_resource_nr_samples(&dst->base);
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sx1 = sbox->x * nr_samples;
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sy1 = sbox->y;
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@ -583,9 +579,6 @@ emit_blit_or_clear_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
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}
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}
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if (dtile != stile)
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blit_cntl |= 0x20000000;
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if (info->scissor_enable) {
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OUT_PKT4(ring, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
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OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(info->scissor.minx) |
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