freedreno/a6xx: Don't set unknown bit when tiling differs

There is a bit here that's sometimes set, but it's generally not
related to whether tiling differs between src and dst.  Let's stop
setting it until we know more.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5717>
This commit is contained in:
Kristian H. Kristensen 2020-07-02 03:49:57 -07:00 committed by Marge Bot
parent def7e7426d
commit 25bfc3b049
1 changed files with 0 additions and 7 deletions

View File

@ -496,7 +496,6 @@ emit_blit_or_clear_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
const struct pipe_box *dbox = &info->dst.box;
struct fd_resource *dst;
enum a6xx_format sfmt, dfmt;
enum a6xx_tile_mode stile, dtile;
int sx1, sy1, sx2, sy2;
int dx1, dy1, dx2, dy2;
@ -515,9 +514,6 @@ emit_blit_or_clear_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
sfmt = fd6_pipe2color(info->src.format);
dfmt = fd6_pipe2color(info->dst.format);
stile = fd_resource_tile_mode(info->src.resource, info->src.level);
dtile = fd_resource_tile_mode(info->dst.resource, info->dst.level);
uint32_t nr_samples = fd_resource_nr_samples(&dst->base);
sx1 = sbox->x * nr_samples;
sy1 = sbox->y;
@ -583,9 +579,6 @@ emit_blit_or_clear_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
}
}
if (dtile != stile)
blit_cntl |= 0x20000000;
if (info->scissor_enable) {
OUT_PKT4(ring, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(info->scissor.minx) |