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i965: Remove the gen6 emit_mi_flushes I sprinkled around the driver. 

These were for debugging in bringup.  Now that relatively complicated
apps are working, they haven't helped debug anything in quite a while.
This commit is contained in:
Eric Anholt 2010-10-19 09:50:44 -07:00
parent 32573792de
commit 2595589f1d
10 changed files with 0 additions and 26 deletions
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2
src/mesa/drivers/dri/i965/brw_misc_state.c
View File

@ -515,8 +515,6 @@ static void upload_invarient_state( struct brw_context *brw )
if (intel->gen >= 6) {
int i;
intel_batchbuffer_emit_mi_flush(intel->batch);
BEGIN_BATCH(3);
OUT_BATCH(CMD_3D_MULTISAMPLE << 16 | (3 - 2));
OUT_BATCH(MS_PIXEL_LOCATION_CENTER |

2
src/mesa/drivers/dri/i965/gen6_cc.c
View File

@ -271,8 +271,6 @@ static void upload_cc_state_pointers(struct brw_context *brw)
OUT_RELOC(brw->cc.depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(intel->batch);
}

2
src/mesa/drivers/dri/i965/gen6_clip_state.c
View File

@ -61,8 +61,6 @@ upload_clip_state(struct brw_context *brw)
provoking);
OUT_BATCH(GEN6_CLIP_FORCE_ZERO_RTAINDEX);
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(intel->batch);
}
const struct brw_tracked_state gen6_clip_state = {

2
src/mesa/drivers/dri/i965/gen6_gs_state.c
View File

@ -44,8 +44,6 @@ upload_gs_state(struct brw_context *brw)
OUT_BATCH(0);
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(intel->batch);
if (brw->gs.prog_bo) {
BEGIN_BATCH(7);
OUT_BATCH(CMD_3D_GS_STATE << 16 | (7 - 2));

2
src/mesa/drivers/dri/i965/gen6_sampler_state.c
View File

@ -49,8 +49,6 @@ upload_sampler_state_pointers(struct brw_context *brw)
OUT_BATCH(0);
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(intel->batch);
}

2
src/mesa/drivers/dri/i965/gen6_sf_state.c
View File

@ -187,8 +187,6 @@ upload_sf_state(struct brw_context *brw)
OUT_BATCH(0); /* wrapshortest enables 0-7 */
OUT_BATCH(0); /* wrapshortest enables 8-15 */
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(intel->batch);
}
const struct brw_tracked_state gen6_sf_state = {

4
src/mesa/drivers/dri/i965/gen6_urb.c
View File

@ -59,8 +59,6 @@ upload_urb(struct brw_context *brw)
/* GS requirement */
assert(!brw->gs.prog_bo || brw->urb.vs_size < 5);
intel_batchbuffer_emit_mi_flush(intel->batch);
BEGIN_BATCH(3);
OUT_BATCH(CMD_URB << 16 | (3 - 2));
OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) |
@ -68,8 +66,6 @@ upload_urb(struct brw_context *brw)
OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |
((brw->urb.nr_gs_entries) << GEN6_URB_GS_ENTRIES_SHIFT));
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(intel->batch);
}
const struct brw_tracked_state gen6_urb = {

2
src/mesa/drivers/dri/i965/gen6_viewport_state.c
View File

@ -125,8 +125,6 @@ static void upload_viewport_state_pointers(struct brw_context *brw)
OUT_RELOC(brw->sf.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
OUT_RELOC(brw->cc.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(intel->batch);
}
const struct brw_tracked_state gen6_viewport_state = {

4
src/mesa/drivers/dri/i965/gen6_vs_state.c
View File

@ -88,8 +88,6 @@ upload_vs_state(struct brw_context *brw)
drm_intel_bo_unreference(constant_bo);
}
intel_batchbuffer_emit_mi_flush(intel->batch);
BEGIN_BATCH(6);
OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2));
OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
@ -103,8 +101,6 @@ upload_vs_state(struct brw_context *brw)
GEN6_VS_STATISTICS_ENABLE |
GEN6_VS_ENABLE);
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(intel->batch);
}
const struct brw_tracked_state gen6_vs_state = {

4
src/mesa/drivers/dri/i965/gen6_wm_state.c
View File

@ -109,8 +109,6 @@ upload_wm_state(struct brw_context *brw)
ADVANCE_BATCH();
}
intel_batchbuffer_emit_mi_flush(intel->batch);
dw2 = dw4 = dw5 = dw6 = 0;
dw4 |= GEN6_WM_STATISTICS_ENABLE;
dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
@ -167,8 +165,6 @@ upload_wm_state(struct brw_context *brw)
OUT_BATCH(0); /* kernel 1 pointer */
OUT_BATCH(0); /* kernel 2 pointer */
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(intel->batch);
}
const struct brw_tracked_state gen6_wm_state = {