radeonsi/tmz: add tmz variant of sctx::wait_mem_scratch
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6049>
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@ -196,6 +196,7 @@ static void si_destroy_context(struct pipe_context *context)
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si_resource_reference(&sctx->scratch_buffer, NULL);
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si_resource_reference(&sctx->scratch_buffer, NULL);
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si_resource_reference(&sctx->compute_scratch_buffer, NULL);
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si_resource_reference(&sctx->compute_scratch_buffer, NULL);
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si_resource_reference(&sctx->wait_mem_scratch, NULL);
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si_resource_reference(&sctx->wait_mem_scratch, NULL);
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si_resource_reference(&sctx->wait_mem_scratch_tmz, NULL);
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si_resource_reference(&sctx->small_prim_cull_info_buf, NULL);
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si_resource_reference(&sctx->small_prim_cull_info_buf, NULL);
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if (sctx->cs_preamble_state)
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if (sctx->cs_preamble_state)
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@ -619,6 +620,17 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
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sscreen->info.tcc_cache_line_size);
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sscreen->info.tcc_cache_line_size);
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if (!sctx->wait_mem_scratch)
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if (!sctx->wait_mem_scratch)
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goto fail;
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goto fail;
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if (sscreen->info.has_tmz_support) {
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sctx->wait_mem_scratch_tmz =
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si_aligned_buffer_create(screen,
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SI_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL |
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PIPE_RESOURCE_FLAG_ENCRYPTED,
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PIPE_USAGE_DEFAULT, 8,
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sscreen->info.tcc_cache_line_size);
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if (!sctx->wait_mem_scratch_tmz)
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goto fail;
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}
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}
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}
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/* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
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/* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
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@ -692,10 +704,12 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
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assert(sctx->gfx_cs->current.cdw == sctx->initial_gfx_cs_size);
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assert(sctx->gfx_cs->current.cdw == sctx->initial_gfx_cs_size);
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/* Initialize per-context buffers. */
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/* Initialize per-context buffers. */
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if (sctx->wait_mem_scratch) {
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if (sctx->wait_mem_scratch)
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si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4, V_370_MEM, V_370_ME,
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si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4, V_370_MEM, V_370_ME,
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&sctx->wait_mem_number);
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&sctx->wait_mem_number);
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}
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if (sctx->wait_mem_scratch_tmz)
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si_cp_write_data(sctx, sctx->wait_mem_scratch_tmz, 0, 4, V_370_MEM, V_370_ME,
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&sctx->wait_mem_number);
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if (sctx->chip_class == GFX7) {
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if (sctx->chip_class == GFX7) {
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/* Clear the NULL constant buffer, because loads should return zeros.
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/* Clear the NULL constant buffer, because loads should return zeros.
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@ -951,6 +951,7 @@ struct si_context {
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struct si_shader_ctx_state fixed_func_tcs_shader;
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struct si_shader_ctx_state fixed_func_tcs_shader;
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/* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
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/* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
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struct si_resource *wait_mem_scratch;
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struct si_resource *wait_mem_scratch;
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struct si_resource *wait_mem_scratch_tmz;
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unsigned wait_mem_number;
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unsigned wait_mem_number;
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uint16_t prefetch_L2_mask;
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uint16_t prefetch_L2_mask;
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@ -1112,6 +1112,8 @@ void gfx10_emit_cache_flush(struct si_context *ctx)
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}
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}
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if (cb_db_event) {
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if (cb_db_event) {
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struct si_resource* wait_mem_scratch = unlikely(ctx->ws->cs_is_secure(cs)) ?
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ctx->wait_mem_scratch_tmz : ctx->wait_mem_scratch;
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/* CB/DB flush and invalidate (or possibly just a wait for a
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/* CB/DB flush and invalidate (or possibly just a wait for a
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* meta flush) via RELEASE_MEM.
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* meta flush) via RELEASE_MEM.
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*
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*
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@ -1123,7 +1125,7 @@ void gfx10_emit_cache_flush(struct si_context *ctx)
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uint64_t va;
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uint64_t va;
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/* Do the flush (enqueue the event and wait for it). */
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/* Do the flush (enqueue the event and wait for it). */
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va = ctx->wait_mem_scratch->gpu_address;
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va = wait_mem_scratch->gpu_address;
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ctx->wait_mem_number++;
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ctx->wait_mem_number++;
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/* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
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/* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
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@ -1146,7 +1148,7 @@ void gfx10_emit_cache_flush(struct si_context *ctx)
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S_490_GL1_INV(gl1_inv) | S_490_GL2_INV(gl2_inv) | S_490_GL2_WB(gl2_wb) |
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S_490_GL1_INV(gl1_inv) | S_490_GL2_INV(gl2_inv) | S_490_GL2_WB(gl2_wb) |
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S_490_SEQ(gcr_seq),
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S_490_SEQ(gcr_seq),
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EOP_DST_SEL_MEM, EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
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EOP_DST_SEL_MEM, EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
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EOP_DATA_SEL_VALUE_32BIT, ctx->wait_mem_scratch, va, ctx->wait_mem_number,
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EOP_DATA_SEL_VALUE_32BIT, wait_mem_scratch, va, ctx->wait_mem_number,
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SI_NOT_QUERY);
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SI_NOT_QUERY);
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si_cp_wait_mem(ctx, ctx->gfx_cs, va, ctx->wait_mem_number, 0xffffffff, WAIT_REG_MEM_EQUAL);
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si_cp_wait_mem(ctx, ctx->gfx_cs, va, ctx->wait_mem_number, 0xffffffff, WAIT_REG_MEM_EQUAL);
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}
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}
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@ -1340,12 +1342,14 @@ void si_emit_cache_flush(struct si_context *sctx)
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}
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}
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/* Do the flush (enqueue the event and wait for it). */
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/* Do the flush (enqueue the event and wait for it). */
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va = sctx->wait_mem_scratch->gpu_address;
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struct si_resource* wait_mem_scratch = unlikely(sctx->ws->cs_is_secure(cs)) ?
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sctx->wait_mem_scratch_tmz : sctx->wait_mem_scratch;
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va = wait_mem_scratch->gpu_address;
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sctx->wait_mem_number++;
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sctx->wait_mem_number++;
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si_cp_release_mem(sctx, cs, cb_db_event, tc_flags, EOP_DST_SEL_MEM,
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si_cp_release_mem(sctx, cs, cb_db_event, tc_flags, EOP_DST_SEL_MEM,
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EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_VALUE_32BIT,
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EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_VALUE_32BIT,
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sctx->wait_mem_scratch, va, sctx->wait_mem_number, SI_NOT_QUERY);
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wait_mem_scratch, va, sctx->wait_mem_number, SI_NOT_QUERY);
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si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff, WAIT_REG_MEM_EQUAL);
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si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff, WAIT_REG_MEM_EQUAL);
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}
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}
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