i965: fix depth test on sandybridge
This includes several corrections for fixing depth test on sandybridge. Fix wrong bits definition in depth stencil state. Fix wrong order of state buffer offset in 3DSTATE_CC_STATE_POINTERS command. Correctly use buffer width parameter in depth buffer setting. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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@ -295,7 +295,7 @@ static void emit_depthbuffer(struct brw_context *brw)
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
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0);
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OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
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((region->pitch - 1) << 6) |
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((region->width - 1) << 6) |
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((region->height - 1) << 19));
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OUT_BATCH(0);
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@ -750,7 +750,7 @@ struct gen6_depth_stencil_state
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} ds1;
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struct {
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GLuint pad0:25;
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GLuint pad0:26;
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GLuint depth_write_enable:1;
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GLuint depth_test_func:3;
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GLuint pad1:1;
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@ -267,9 +267,9 @@ static void upload_cc_state_pointers(struct brw_context *brw)
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BEGIN_BATCH(4);
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OUT_BATCH(CMD_3D_CC_STATE_POINTERS << 16 | (4 - 2));
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OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
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OUT_RELOC(brw->cc.blend_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
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OUT_RELOC(brw->cc.depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
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OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
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ADVANCE_BATCH();
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intel_batchbuffer_emit_mi_flush(intel->batch);
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