r600g: rework flusing and synchronization pattern v7
This bring r600g allmost inline with closed source driver when it comes to flushing and synchronization pattern. v2-v4: history lost somewhere in outer space v5: Fix compute size of flushing, use define for flags, update worst case cs size requirement for flush, treat rs780 and newer as r7xx when it comes to streamout. v6: Fix num dw computation for framebuffer state, remove dead code, use define instead of hardcoded value. v7: Remove dead code Signed-off-by: Jerome Glisse <jglisse@redhat.com>
This commit is contained in:
parent
cf5632094b
commit
24b1206ab2
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@ -98,7 +98,7 @@ static void evergreen_cs_set_vertex_buffer(
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/* The vertex instructions in the compute shaders use the texture cache,
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* so we need to invalidate it. */
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rctx->flags |= R600_CONTEXT_TEX_FLUSH;
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rctx->flags |= R600_CONTEXT_GPU_FLUSH;
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state->enabled_mask |= 1 << vb_index;
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state->dirty_mask |= 1 << vb_index;
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state->atom.dirty = true;
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@ -329,7 +329,7 @@ static void compute_emit_cs(struct r600_context *ctx, const uint *block_layout,
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*/
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r600_emit_command_buffer(ctx->cs, &ctx->start_compute_cs_cmd);
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ctx->flags |= R600_CONTEXT_CB_FLUSH;
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ctx->flags |= R600_CONTEXT_WAIT_IDLE | R600_CONTEXT_FLUSH_AND_INV;
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r600_flush_emit(ctx);
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/* Emit colorbuffers. */
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@ -409,7 +409,7 @@ static void compute_emit_cs(struct r600_context *ctx, const uint *block_layout,
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/* XXX evergreen_flush_emit() hardcodes the CP_COHER_SIZE to 0xffffffff
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*/
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ctx->flags |= R600_CONTEXT_CB_FLUSH;
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ctx->flags |= R600_CONTEXT_GPU_FLUSH;
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r600_flush_emit(ctx);
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#if 0
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@ -468,7 +468,7 @@ void evergreen_emit_cs_shader(
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r600_write_value(cs, r600_context_bo_reloc(rctx, kernel->code_bo,
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RADEON_USAGE_READ));
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rctx->flags |= R600_CONTEXT_SHADERCONST_FLUSH;
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rctx->flags |= R600_CONTEXT_GPU_FLUSH;
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}
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static void evergreen_launch_grid(
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@ -545,7 +545,7 @@ void evergreen_set_tex_resource(
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util_format_get_blockwidth(tmp->resource.b.b.format) *
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view->base.texture->width0*height*depth;
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pipe->ctx->flags |= R600_CONTEXT_TEX_FLUSH;
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pipe->ctx->flags |= R600_CONTEXT_GPU_FLUSH;
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evergreen_emit_force_reloc(res);
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evergreen_emit_force_reloc(res);
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@ -604,7 +604,7 @@ void evergreen_set_const_cache(
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res->usage = RADEON_USAGE_READ;
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res->coher_bo_size = size;
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pipe->ctx->flags |= R600_CONTEXT_SHADERCONST_FLUSH;
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pipe->ctx->flags |= R600_CONTEXT_GPU_FLUSH;
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}
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struct r600_resource* r600_compute_buffer_alloc_vram(
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@ -1557,14 +1557,14 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
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uint32_t i, log_samples;
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if (rctx->framebuffer.state.nr_cbufs) {
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rctx->flags |= R600_CONTEXT_CB_FLUSH;
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rctx->flags |= R600_CONTEXT_WAIT_IDLE | R600_CONTEXT_FLUSH_AND_INV;
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if (rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
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rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
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}
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}
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if (rctx->framebuffer.state.zsbuf) {
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rctx->flags |= R600_CONTEXT_DB_FLUSH;
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rctx->flags |= R600_CONTEXT_WAIT_IDLE | R600_CONTEXT_FLUSH_AND_INV;
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}
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util_copy_framebuffer_state(&rctx->framebuffer.state, state);
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@ -182,17 +182,11 @@ struct r600_so_target {
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unsigned so_index;
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};
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#define R600_CONTEXT_PS_PARTIAL_FLUSH (1 << 0)
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#define R600_CONTEXT_CB_FLUSH (1 << 1)
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#define R600_CONTEXT_DB_FLUSH (1 << 2)
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#define R600_CONTEXT_SHADERCONST_FLUSH (1 << 3)
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#define R600_CONTEXT_TEX_FLUSH (1 << 4)
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#define R600_CONTEXT_VTX_FLUSH (1 << 5)
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#define R600_CONTEXT_STREAMOUT_FLUSH (1 << 6)
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#define R600_CONTEXT_WAIT_IDLE (1 << 7)
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#define R600_CONTEXT_FLUSH_AND_INV (1 << 8)
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#define R600_CONTEXT_HTILE_ERRATA (1 << 9)
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#define R600_CONTEXT_FLUSH_AND_INV_CB_META (1 << 10)
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#define R600_CONTEXT_GPU_FLUSH (1 << 0)
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#define R600_CONTEXT_STREAMOUT_FLUSH (1 << 1)
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#define R600_CONTEXT_WAIT_IDLE (1 << 2)
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#define R600_CONTEXT_FLUSH_AND_INV (1 << 3)
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#define R600_CONTEXT_FLUSH_AND_INV_CB_META (1 << 4)
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struct r600_context;
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struct r600_screen;
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@ -424,7 +424,7 @@ void r600_context_dirty_block(struct r600_context *ctx,
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LIST_ADDTAIL(&block->list,&ctx->dirty);
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if (block->flags & REG_FLAG_FLUSH_CHANGE) {
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ctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
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ctx->flags |= R600_CONTEXT_WAIT_IDLE;
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}
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}
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}
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@ -595,16 +595,13 @@ out:
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void r600_flush_emit(struct r600_context *rctx)
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{
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struct radeon_winsys_cs *cs = rctx->cs;
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unsigned cp_coher_cntl = 0;
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unsigned emit_flush = 0;
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if (!rctx->flags) {
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return;
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}
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if (rctx->flags & R600_CONTEXT_PS_PARTIAL_FLUSH) {
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cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
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cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
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}
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if (rctx->chip_class >= R700 &&
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(rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
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cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
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@ -614,110 +611,54 @@ void r600_flush_emit(struct r600_context *rctx)
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if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV) {
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cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
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cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
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/* DB flushes are special due to errata with hyperz, we need to
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* insert a no-op, so that the cache has time to really flush.
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*/
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if (rctx->chip_class <= R700 &&
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rctx->flags & R600_CONTEXT_HTILE_ERRATA) {
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cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 31, 0);
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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cs->buf[cs->cdw++] = 0xdeadcafe;
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if (rctx->chip_class >= EVERGREEN) {
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cp_coher_cntl = S_0085F0_CB0_DEST_BASE_ENA(1) |
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S_0085F0_CB1_DEST_BASE_ENA(1) |
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S_0085F0_CB2_DEST_BASE_ENA(1) |
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S_0085F0_CB3_DEST_BASE_ENA(1) |
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S_0085F0_CB4_DEST_BASE_ENA(1) |
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S_0085F0_CB5_DEST_BASE_ENA(1) |
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S_0085F0_CB6_DEST_BASE_ENA(1) |
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S_0085F0_CB7_DEST_BASE_ENA(1) |
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S_0085F0_CB8_DEST_BASE_ENA(1) |
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S_0085F0_CB9_DEST_BASE_ENA(1) |
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S_0085F0_CB10_DEST_BASE_ENA(1) |
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S_0085F0_CB11_DEST_BASE_ENA(1) |
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S_0085F0_DB_DEST_BASE_ENA(1) |
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S_0085F0_TC_ACTION_ENA(1) |
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S_0085F0_CB_ACTION_ENA(1) |
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S_0085F0_DB_ACTION_ENA(1) |
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S_0085F0_SH_ACTION_ENA(1) |
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S_0085F0_SMX_ACTION_ENA(1) |
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(1 << 20); /* unknown bit */
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} else {
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cp_coher_cntl = S_0085F0_SMX_ACTION_ENA(1) |
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S_0085F0_SH_ACTION_ENA(1) |
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S_0085F0_VC_ACTION_ENA(1) |
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S_0085F0_TC_ACTION_ENA(1) |
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(1 << 20); /* unknown bit */
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}
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}
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if (rctx->flags & (R600_CONTEXT_CB_FLUSH |
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R600_CONTEXT_DB_FLUSH |
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R600_CONTEXT_SHADERCONST_FLUSH |
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R600_CONTEXT_TEX_FLUSH |
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R600_CONTEXT_VTX_FLUSH |
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R600_CONTEXT_STREAMOUT_FLUSH)) {
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/* anything left (cb, vtx, shader, streamout) can be flushed
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* using the surface sync packet
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*/
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unsigned flags = 0;
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if (rctx->flags & R600_CONTEXT_GPU_FLUSH) {
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cp_coher_cntl |= S_0085F0_VC_ACTION_ENA(1) |
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S_0085F0_TC_ACTION_ENA(1) |
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(1 << 20); /* unknown bit */
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emit_flush = 1;
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}
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if (rctx->flags & R600_CONTEXT_CB_FLUSH) {
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flags |= S_0085F0_CB_ACTION_ENA(1) |
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S_0085F0_CB0_DEST_BASE_ENA(1) |
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S_0085F0_CB1_DEST_BASE_ENA(1) |
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S_0085F0_CB2_DEST_BASE_ENA(1) |
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S_0085F0_CB3_DEST_BASE_ENA(1) |
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S_0085F0_CB4_DEST_BASE_ENA(1) |
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S_0085F0_CB5_DEST_BASE_ENA(1) |
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S_0085F0_CB6_DEST_BASE_ENA(1) |
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S_0085F0_CB7_DEST_BASE_ENA(1);
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if (rctx->chip_class >= EVERGREEN) {
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flags |= S_0085F0_CB8_DEST_BASE_ENA(1) |
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S_0085F0_CB9_DEST_BASE_ENA(1) |
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S_0085F0_CB10_DEST_BASE_ENA(1) |
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S_0085F0_CB11_DEST_BASE_ENA(1);
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}
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/* RV670 errata
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* (CB1_DEST_BASE_ENA is also required, which is
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* included unconditionally above). */
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if (rctx->family == CHIP_RV670 ||
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rctx->family == CHIP_RS780 ||
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rctx->family == CHIP_RS880) {
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flags |= S_0085F0_DEST_BASE_0_ENA(1);
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}
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}
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if (rctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
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flags |= S_0085F0_SO0_DEST_BASE_ENA(1) |
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S_0085F0_SO1_DEST_BASE_ENA(1) |
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S_0085F0_SO2_DEST_BASE_ENA(1) |
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S_0085F0_SO3_DEST_BASE_ENA(1) |
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S_0085F0_SMX_ACTION_ENA(1);
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/* RV670 errata */
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if (rctx->family == CHIP_RV670 ||
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rctx->family == CHIP_RS780 ||
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rctx->family == CHIP_RS880) {
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flags |= S_0085F0_DEST_BASE_0_ENA(1);
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}
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}
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flags |= (rctx->flags & R600_CONTEXT_DB_FLUSH) ? S_0085F0_DB_ACTION_ENA(1) |
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S_0085F0_DB_DEST_BASE_ENA(1): 0;
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flags |= (rctx->flags & R600_CONTEXT_SHADERCONST_FLUSH) ? S_0085F0_SH_ACTION_ENA(1) : 0;
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flags |= (rctx->flags & R600_CONTEXT_TEX_FLUSH) ? S_0085F0_TC_ACTION_ENA(1) : 0;
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flags |= (rctx->flags & R600_CONTEXT_VTX_FLUSH) ? S_0085F0_VC_ACTION_ENA(1) : 0;
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if (rctx->family >= CHIP_RV770 && rctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
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cp_coher_cntl |= S_0085F0_SO0_DEST_BASE_ENA(1) |
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S_0085F0_SO1_DEST_BASE_ENA(1) |
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S_0085F0_SO2_DEST_BASE_ENA(1) |
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S_0085F0_SO3_DEST_BASE_ENA(1) |
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S_0085F0_SMX_ACTION_ENA(1);
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emit_flush = 1;
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}
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if (emit_flush) {
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cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
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cs->buf[cs->cdw++] = flags; /* CP_COHER_CNTL */
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cs->buf[cs->cdw++] = cp_coher_cntl; /* CP_COHER_CNTL */
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cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
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cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
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cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
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@ -758,16 +699,10 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
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ctx->streamout_suspended = true;
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}
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/* partial flush is needed to avoid lockups on some chips with user fences */
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ctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
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/* flush the framebuffer */
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ctx->flags |= R600_CONTEXT_CB_FLUSH | R600_CONTEXT_DB_FLUSH;
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/* R6xx errata */
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if (ctx->chip_class == R600) {
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ctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
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}
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/* flush is needed to avoid lockups on some chips with user fences
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* this will also flush the framebuffer cache
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*/
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ctx->flags |= R600_CONTEXT_WAIT_IDLE | R600_CONTEXT_FLUSH_AND_INV;
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r600_flush_emit(ctx);
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@ -884,9 +819,7 @@ void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fen
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va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
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va = va + (offset << 2);
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ctx->flags &= ~R600_CONTEXT_PS_PARTIAL_FLUSH;
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cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
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cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
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r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
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cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
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cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
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@ -1073,15 +1006,14 @@ void r600_context_streamout_end(struct r600_context *ctx)
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}
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if (ctx->chip_class >= EVERGREEN) {
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ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
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evergreen_set_streamout_enable(ctx, 0);
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} else {
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if (ctx->chip_class >= R700) {
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ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
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}
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r600_set_streamout_enable(ctx, 0);
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}
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ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
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/* R6xx errata */
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if (ctx->chip_class == R600) {
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ctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
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}
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ctx->flags |= R600_CONTEXT_WAIT_IDLE | R600_CONTEXT_FLUSH_AND_INV;
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ctx->num_cs_dw_streamout_end = 0;
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}
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@ -29,7 +29,7 @@
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#include "r600_pipe.h"
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/* the number of CS dwords for flushing and drawing */
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#define R600_MAX_FLUSH_CS_DWORDS 46
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#define R600_MAX_FLUSH_CS_DWORDS 12
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#define R600_MAX_DRAW_CS_DWORDS 34
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/* these flags are used in register flags and added into block flags */
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@ -1452,7 +1452,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
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unsigned i;
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if (rctx->framebuffer.state.nr_cbufs) {
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rctx->flags |= R600_CONTEXT_CB_FLUSH;
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rctx->flags |= R600_CONTEXT_WAIT_IDLE | R600_CONTEXT_FLUSH_AND_INV;
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if (rctx->chip_class >= R700 &&
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rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
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@ -1460,11 +1460,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
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}
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}
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if (rctx->framebuffer.state.zsbuf) {
|
||||
rctx->flags |= R600_CONTEXT_DB_FLUSH;
|
||||
}
|
||||
/* R6xx errata */
|
||||
if (rctx->chip_class == R600) {
|
||||
rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
|
||||
rctx->flags |= R600_CONTEXT_WAIT_IDLE | R600_CONTEXT_FLUSH_AND_INV;
|
||||
}
|
||||
|
||||
/* Set the new state. */
|
||||
|
@ -1558,7 +1554,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
|
|||
|
||||
}
|
||||
if (rctx->framebuffer.state.zsbuf) {
|
||||
rctx->framebuffer.atom.num_dw += 16;
|
||||
rctx->framebuffer.atom.num_dw += 18;
|
||||
} else if (rctx->screen->info.drm_minor >= 18) {
|
||||
rctx->framebuffer.atom.num_dw += 3;
|
||||
}
|
||||
|
@ -1742,6 +1738,13 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a
|
|||
sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
|
||||
}
|
||||
|
||||
/* SURFACE_BASE_UPDATE */
|
||||
if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770 && sbu) {
|
||||
r600_write_value(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
|
||||
r600_write_value(cs, sbu);
|
||||
sbu = 0;
|
||||
}
|
||||
|
||||
/* Zbuffer. */
|
||||
if (state->zsbuf) {
|
||||
struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
|
||||
|
@ -1775,6 +1778,7 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a
|
|||
if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770 && sbu) {
|
||||
r600_write_value(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
|
||||
r600_write_value(cs, sbu);
|
||||
sbu = 0;
|
||||
}
|
||||
|
||||
/* Framebuffer dimensions. */
|
||||
|
@ -2243,7 +2247,7 @@ bool r600_adjust_gprs(struct r600_context *rctx)
|
|||
if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp) {
|
||||
rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
|
||||
rctx->config_state.atom.dirty = true;
|
||||
rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
|
||||
rctx->flags |= R600_CONTEXT_WAIT_IDLE;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
|
|
@ -88,12 +88,9 @@ static void r600_texture_barrier(struct pipe_context *ctx)
|
|||
{
|
||||
struct r600_context *rctx = (struct r600_context *)ctx;
|
||||
|
||||
rctx->flags |= R600_CONTEXT_CB_FLUSH | R600_CONTEXT_TEX_FLUSH;
|
||||
|
||||
/* R6xx errata */
|
||||
if (rctx->chip_class == R600) {
|
||||
rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
|
||||
}
|
||||
rctx->flags |= R600_CONTEXT_WAIT_IDLE;
|
||||
rctx->flags |= R600_CONTEXT_GPU_FLUSH;
|
||||
rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
|
||||
}
|
||||
|
||||
static unsigned r600_conv_pipe_prim(unsigned prim)
|
||||
|
@ -360,7 +357,7 @@ void r600_sampler_states_dirty(struct r600_context *rctx,
|
|||
{
|
||||
if (state->dirty_mask) {
|
||||
if (state->dirty_mask & state->has_bordercolor_mask) {
|
||||
rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
|
||||
rctx->flags |= R600_CONTEXT_WAIT_IDLE;
|
||||
}
|
||||
state->atom.num_dw =
|
||||
util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
|
||||
|
@ -423,7 +420,7 @@ static void r600_bind_sampler_states(struct pipe_context *pipe,
|
|||
seamless_cube_map != -1 &&
|
||||
seamless_cube_map != rctx->seamless_cube_map.enabled) {
|
||||
/* change in TA_CNTL_AUX need a pipeline flush */
|
||||
rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
|
||||
rctx->flags |= R600_CONTEXT_WAIT_IDLE;
|
||||
rctx->seamless_cube_map.enabled = seamless_cube_map;
|
||||
rctx->seamless_cube_map.atom.dirty = true;
|
||||
}
|
||||
|
@ -491,7 +488,7 @@ static void r600_set_index_buffer(struct pipe_context *ctx,
|
|||
void r600_vertex_buffers_dirty(struct r600_context *rctx)
|
||||
{
|
||||
if (rctx->vertex_buffer_state.dirty_mask) {
|
||||
rctx->flags |= rctx->has_vertex_cache ? R600_CONTEXT_VTX_FLUSH : R600_CONTEXT_TEX_FLUSH;
|
||||
rctx->flags |= R600_CONTEXT_GPU_FLUSH;
|
||||
rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
|
||||
util_bitcount(rctx->vertex_buffer_state.dirty_mask);
|
||||
rctx->vertex_buffer_state.atom.dirty = true;
|
||||
|
@ -547,7 +544,7 @@ void r600_sampler_views_dirty(struct r600_context *rctx,
|
|||
struct r600_samplerview_state *state)
|
||||
{
|
||||
if (state->dirty_mask) {
|
||||
rctx->flags |= R600_CONTEXT_TEX_FLUSH;
|
||||
rctx->flags |= R600_CONTEXT_GPU_FLUSH;
|
||||
state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
|
||||
util_bitcount(state->dirty_mask);
|
||||
state->atom.dirty = true;
|
||||
|
@ -889,7 +886,7 @@ static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
|
|||
void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
|
||||
{
|
||||
if (state->dirty_mask) {
|
||||
rctx->flags |= R600_CONTEXT_SHADERCONST_FLUSH;
|
||||
rctx->flags |= R600_CONTEXT_GPU_FLUSH;
|
||||
state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
|
||||
: util_bitcount(state->dirty_mask)*19;
|
||||
state->atom.dirty = true;
|
||||
|
|
Loading…
Reference in New Issue