radv: Implement mesh shading draw calls with task shaders.
This implements NV_mesh_shader draw calls with task shaders. - On the GFX side: DISPATCH_TASKMESH_GFX for all draws - On the ACE side: DISPATCH_TASKMESH_DIRECT_ACE for direct draws DISPATCH_TASKMESH_INDIRECT_MULTI_ACE for indirect draws Additionally, the NV_mesh_shader indirect BO layout is incompatible with AMD HW, so we add a function that copies that into a suitable layout. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16531>
This commit is contained in:
Timur Kristóf
Marge Bot
parent
99179f8490
commit
2479b62869
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@ -6375,7 +6375,7 @@ radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
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{
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struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
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radv_foreach_stage(stage, pipeline->active_stages) {
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radv_foreach_stage(stage, pipeline->active_stages & ~VK_SHADER_STAGE_TASK_BIT_NV) {
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radv_emit_view_index_per_stage(cmd_buffer->cs, pipeline, stage, index);
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}
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if (radv_pipeline_has_gs_copy_shader(&pipeline->base)) {
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@ -6386,6 +6386,10 @@ radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
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radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
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}
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}
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if (pipeline->active_stages & VK_SHADER_STAGE_TASK_BIT_NV) {
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radv_emit_view_index_per_stage(cmd_buffer->ace_internal.cs, pipeline, MESA_SHADER_TASK,
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index);
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}
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}
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/**
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@ -6529,6 +6533,109 @@ radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer, bool index
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}
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}
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ALWAYS_INLINE static void
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radv_cs_emit_dispatch_taskmesh_direct_ace_packet(struct radv_cmd_buffer *cmd_buffer,
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const uint32_t x, const uint32_t y,
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const uint32_t z)
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{
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struct radv_pipeline *pipeline = &cmd_buffer->state.graphics_pipeline->base;
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struct radv_shader *compute_shader = radv_get_shader(pipeline, MESA_SHADER_TASK);
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struct radeon_cmdbuf *cs = cmd_buffer->ace_internal.cs;
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const bool predicating = cmd_buffer->state.predicating;
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const uint32_t dispatch_initiator = cmd_buffer->device->dispatch_initiator_task |
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S_00B800_CS_W32_EN(compute_shader->info.wave_size == 32);
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struct radv_userdata_info *ring_entry_loc =
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radv_lookup_user_sgpr(pipeline, MESA_SHADER_TASK, AC_UD_TASK_RING_ENTRY);
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assert(ring_entry_loc && ring_entry_loc->sgpr_idx != -1 && ring_entry_loc->num_sgprs == 1);
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uint32_t ring_entry_reg =
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(R_00B900_COMPUTE_USER_DATA_0 + ring_entry_loc->sgpr_idx * 4 - SI_SH_REG_OFFSET) >> 2;
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radeon_emit(cs, PKT3(PKT3_DISPATCH_TASKMESH_DIRECT_ACE, 4, predicating) | PKT3_SHADER_TYPE_S(1));
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radeon_emit(cs, x);
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radeon_emit(cs, y);
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radeon_emit(cs, z);
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radeon_emit(cs, dispatch_initiator);
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radeon_emit(cs, ring_entry_reg & 0xFFFF);
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}
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ALWAYS_INLINE static void
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radv_cs_emit_dispatch_taskmesh_indirect_multi_ace_packet(struct radv_cmd_buffer *cmd_buffer,
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uint64_t data_va, uint32_t draw_count,
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uint64_t count_va, uint32_t stride)
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{
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assert((data_va & 0x03) == 0);
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assert((count_va & 0x03) == 0);
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struct radv_pipeline *pipeline = &cmd_buffer->state.graphics_pipeline->base;
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struct radv_shader *compute_shader = radv_get_shader(pipeline, MESA_SHADER_TASK);
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struct radeon_cmdbuf *cs = cmd_buffer->ace_internal.cs;
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const uint32_t count_indirect_enable = !!count_va;
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const uint32_t xyz_dim_enable = compute_shader->info.cs.uses_grid_size;
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const uint32_t draw_id_enable = compute_shader->info.vs.needs_draw_id;
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const uint32_t dispatch_initiator = cmd_buffer->device->dispatch_initiator_task |
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S_00B800_CS_W32_EN(compute_shader->info.wave_size == 32);
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const struct radv_userdata_info *ring_entry_loc =
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radv_lookup_user_sgpr(pipeline, MESA_SHADER_TASK, AC_UD_TASK_RING_ENTRY);
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const struct radv_userdata_info *xyz_dim_loc =
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radv_lookup_user_sgpr(pipeline, MESA_SHADER_TASK, AC_UD_CS_GRID_SIZE);
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const struct radv_userdata_info *draw_id_loc =
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radv_lookup_user_sgpr(pipeline, MESA_SHADER_TASK, AC_UD_CS_TASK_DRAW_ID);
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assert(ring_entry_loc->sgpr_idx != -1 && ring_entry_loc->num_sgprs == 1);
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assert(!xyz_dim_enable || (xyz_dim_loc->sgpr_idx != -1 && xyz_dim_loc->num_sgprs == 3));
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assert(!draw_id_enable || (draw_id_loc->sgpr_idx != -1 && draw_id_loc->num_sgprs == 1));
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const uint32_t ring_entry_reg =
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(R_00B900_COMPUTE_USER_DATA_0 + ring_entry_loc->sgpr_idx * 4 - SI_SH_REG_OFFSET) >> 2;
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const uint32_t xyz_dim_reg =
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!xyz_dim_enable
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? 0
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: (R_00B900_COMPUTE_USER_DATA_0 + xyz_dim_loc->sgpr_idx * 4 - SI_SH_REG_OFFSET) >> 2;
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const uint32_t draw_id_reg =
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!draw_id_enable
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? 0
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: (R_00B900_COMPUTE_USER_DATA_0 + draw_id_loc->sgpr_idx * 4 - SI_SH_REG_OFFSET) >> 2;
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radeon_emit(cs, PKT3(PKT3_DISPATCH_TASKMESH_INDIRECT_MULTI_ACE, 9, 0) | PKT3_SHADER_TYPE_S(1));
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radeon_emit(cs, data_va);
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radeon_emit(cs, data_va >> 32);
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radeon_emit(cs, ring_entry_reg & 0xFFFF);
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radeon_emit(cs, (count_indirect_enable << 1) | (draw_id_enable << 2) | (xyz_dim_enable << 3) |
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(draw_id_reg << 16));
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radeon_emit(cs, xyz_dim_reg & 0xFFFF);
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radeon_emit(cs, draw_count);
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radeon_emit(cs, count_va);
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radeon_emit(cs, count_va >> 32);
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radeon_emit(cs, stride);
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radeon_emit(cs, dispatch_initiator);
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}
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ALWAYS_INLINE static void
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radv_cs_emit_dispatch_taskmesh_gfx_packet(struct radv_cmd_buffer *cmd_buffer)
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{
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struct radv_pipeline *pipeline = &cmd_buffer->state.graphics_pipeline->base;
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struct radeon_cmdbuf *cs = cmd_buffer->cs;
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bool predicating = cmd_buffer->state.predicating;
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struct radv_userdata_info *ring_entry_loc =
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radv_lookup_user_sgpr(pipeline, MESA_SHADER_MESH, AC_UD_TASK_RING_ENTRY);
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assert(ring_entry_loc && ring_entry_loc->sgpr_idx != -1);
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uint32_t base_reg = cmd_buffer->state.graphics_pipeline->vtx_base_sgpr;
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uint32_t xyz_dim_reg = ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2;
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uint32_t ring_entry_reg = ((base_reg + ring_entry_loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2;
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radeon_emit(cs, PKT3(PKT3_DISPATCH_TASKMESH_GFX, 2, predicating));
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radeon_emit(cs, (ring_entry_reg << 16) | (xyz_dim_reg & 0xFFFF));
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radeon_emit(cs, 0);
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radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
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}
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static inline void
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radv_emit_userdata_vertex_internal(struct radv_cmd_buffer *cmd_buffer,
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const struct radv_draw_info *info, const uint32_t vertex_offset)
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@ -6606,6 +6713,77 @@ radv_emit_userdata_mesh(struct radv_cmd_buffer *cmd_buffer,
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}
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}
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ALWAYS_INLINE static void
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radv_emit_userdata_mesh_first_task_0_draw_id_0(struct radv_cmd_buffer *cmd_buffer)
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{
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struct radv_cmd_state *state = &cmd_buffer->state;
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struct radeon_cmdbuf *cs = cmd_buffer->cs;
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struct radv_graphics_pipeline *pipeline = state->graphics_pipeline;
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const bool uses_drawid = pipeline->uses_drawid;
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radeon_set_sh_reg_seq(cs, pipeline->vtx_base_sgpr, 1);
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radeon_emit(cs, 0);
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if (uses_drawid) {
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radeon_set_sh_reg_seq(cs, pipeline->vtx_base_sgpr + (pipeline->vtx_emit_num - 1) * 4, 1);
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radeon_emit(cs, 0);
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}
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}
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ALWAYS_INLINE static void
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radv_emit_userdata_task_ib_only(struct radv_cmd_buffer *cmd_buffer, uint64_t ib_va,
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uint32_t ib_stride)
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{
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struct radv_pipeline *pipeline = &cmd_buffer->state.graphics_pipeline->base;
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struct radeon_cmdbuf *cs = cmd_buffer->ace_internal.cs;
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struct radv_userdata_info *task_ib_loc =
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radv_lookup_user_sgpr(pipeline, MESA_SHADER_TASK, AC_UD_CS_TASK_IB);
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if (task_ib_loc->sgpr_idx != -1) {
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assert(task_ib_loc->num_sgprs == 3);
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unsigned task_ib_reg = R_00B900_COMPUTE_USER_DATA_0 + task_ib_loc->sgpr_idx * 4;
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radeon_set_sh_reg_seq(cs, task_ib_reg, 3);
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radeon_emit(cs, ib_va);
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radeon_emit(cs, ib_va >> 32);
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radeon_emit(cs, ib_stride);
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}
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}
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ALWAYS_INLINE static void
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radv_emit_userdata_task(struct radv_cmd_buffer *cmd_buffer, uint32_t x, uint32_t y, uint32_t z,
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uint32_t draw_id, uint32_t first_task, uint64_t ib_va)
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{
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struct radv_pipeline *pipeline = &cmd_buffer->state.graphics_pipeline->base;
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struct radeon_cmdbuf *cs = cmd_buffer->ace_internal.cs;
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struct radv_userdata_info *xyz_loc =
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radv_lookup_user_sgpr(pipeline, MESA_SHADER_TASK, AC_UD_CS_GRID_SIZE);
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struct radv_userdata_info *draw_id_loc =
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radv_lookup_user_sgpr(pipeline, MESA_SHADER_TASK, AC_UD_CS_TASK_DRAW_ID);
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if (xyz_loc->sgpr_idx != -1) {
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assert(xyz_loc->num_sgprs == 3);
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unsigned xyz_reg = R_00B900_COMPUTE_USER_DATA_0 + xyz_loc->sgpr_idx * 4;
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radeon_set_sh_reg_seq(cs, xyz_reg, 3);
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radeon_emit(cs, x);
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radeon_emit(cs, y);
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radeon_emit(cs, z);
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}
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if (draw_id_loc->sgpr_idx != -1) {
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assert(draw_id_loc->num_sgprs == 1);
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unsigned draw_id_reg = R_00B900_COMPUTE_USER_DATA_0 + draw_id_loc->sgpr_idx * 4;
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radeon_set_sh_reg_seq(cs, draw_id_reg, 1);
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radeon_emit(cs, draw_id);
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}
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radv_emit_userdata_task_ib_only(cmd_buffer, ib_va, first_task ? 8 : 0);
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}
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ALWAYS_INLINE static void
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radv_emit_draw_packets_indexed(struct radv_cmd_buffer *cmd_buffer,
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const struct radv_draw_info *info,
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@ -6802,6 +6980,83 @@ radv_emit_direct_mesh_draw_packet(struct radv_cmd_buffer *cmd_buffer,
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}
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}
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ALWAYS_INLINE static void
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radv_emit_direct_taskmesh_draw_packets(struct radv_cmd_buffer *cmd_buffer, uint32_t x, uint32_t y,
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uint32_t z, uint32_t first_task)
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{
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uint64_t fake_ib_va = 0;
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const uint32_t view_mask = cmd_buffer->state.subpass->view_mask;
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const unsigned num_views = MAX2(1, util_bitcount(view_mask));
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unsigned ace_predication_size = num_views * 6; /* DISPATCH_TASKMESH_DIRECT_ACE size */
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if (first_task) {
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/* Pass this as the IB to the shader for emulating firstTask in task shaders. */
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uint32_t fake_ib_dwords[2] = {x, first_task};
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unsigned fake_ib_offset;
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radv_cmd_buffer_upload_data(cmd_buffer, 8, fake_ib_dwords, &fake_ib_offset);
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fake_ib_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + fake_ib_offset;
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}
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radv_emit_userdata_task(cmd_buffer, x, y, z, 0, first_task, fake_ib_va);
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radv_emit_userdata_mesh_first_task_0_draw_id_0(cmd_buffer);
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radv_cs_emit_compute_predication(&cmd_buffer->state, cmd_buffer->ace_internal.cs,
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cmd_buffer->mec_inv_pred_va, &cmd_buffer->mec_inv_pred_emitted,
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ace_predication_size);
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if (!view_mask) {
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radv_cs_emit_dispatch_taskmesh_direct_ace_packet(cmd_buffer, x, y, z);
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radv_cs_emit_dispatch_taskmesh_gfx_packet(cmd_buffer);
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} else {
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u_foreach_bit (view, view_mask) {
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radv_emit_view_index(cmd_buffer, view);
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radv_cs_emit_dispatch_taskmesh_direct_ace_packet(cmd_buffer, x, y, z);
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radv_cs_emit_dispatch_taskmesh_gfx_packet(cmd_buffer);
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}
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}
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}
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static void
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radv_emit_indirect_taskmesh_draw_packets(struct radv_cmd_buffer *cmd_buffer,
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const struct radv_draw_info *info, uint64_t nv_ib_va,
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uint32_t nv_ib_stride)
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{
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const uint32_t view_mask = cmd_buffer->state.subpass->view_mask;
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struct radeon_winsys *ws = cmd_buffer->device->ws;
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const unsigned num_views = MAX2(1, util_bitcount(view_mask));
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unsigned ace_predication_size = num_views * 11; /* DISPATCH_TASKMESH_INDIRECT_MULTI_ACE size */
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const uint64_t va =
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radv_buffer_get_va(info->indirect->bo) + info->indirect->offset + info->indirect_offset;
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const uint64_t count_va = !info->count_buffer
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? 0
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: radv_buffer_get_va(info->count_buffer->bo) +
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info->count_buffer->offset + info->count_buffer_offset;
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if (count_va) {
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radv_cs_add_buffer(ws, cmd_buffer->ace_internal.cs, info->count_buffer->bo);
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}
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radv_cs_add_buffer(ws, cmd_buffer->ace_internal.cs, info->indirect->bo);
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radv_emit_userdata_task_ib_only(cmd_buffer, nv_ib_va, nv_ib_stride);
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radv_emit_userdata_mesh_first_task_0_draw_id_0(cmd_buffer);
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radv_cs_emit_compute_predication(&cmd_buffer->state, cmd_buffer->ace_internal.cs,
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cmd_buffer->mec_inv_pred_va, &cmd_buffer->mec_inv_pred_emitted,
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ace_predication_size);
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if (!view_mask) {
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radv_cs_emit_dispatch_taskmesh_indirect_multi_ace_packet(cmd_buffer, va, info->count,
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count_va, info->stride);
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radv_cs_emit_dispatch_taskmesh_gfx_packet(cmd_buffer);
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} else {
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u_foreach_bit (view, view_mask) {
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radv_emit_view_index(cmd_buffer, view);
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radv_cs_emit_dispatch_taskmesh_indirect_multi_ace_packet(cmd_buffer, va, info->count,
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count_va, info->stride);
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radv_cs_emit_dispatch_taskmesh_gfx_packet(cmd_buffer);
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}
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}
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}
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static void
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radv_emit_indirect_draw_packets(struct radv_cmd_buffer *cmd_buffer,
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const struct radv_draw_info *info)
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@ -7382,6 +7637,77 @@ radv_nv_mesh_indirect_bo(struct radv_cmd_buffer *cmd_buffer,
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return buf;
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}
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static struct radv_buffer
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radv_nv_task_indirect_bo(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buffer,
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VkDeviceSize offset, uint32_t draw_count, uint32_t stride)
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{
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/* Translates the indirect BO format used by NV_mesh_shader API
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* to the BO format used by DISPATCH_TASKMESH_INDIRECT_MULTI_ACE.
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*/
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assert(draw_count);
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static_assert(sizeof(VkDispatchIndirectCommand) == 12, "Incorrect size of taskmesh command.");
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struct radeon_cmdbuf *cs = cmd_buffer->ace_internal.cs;
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struct radeon_winsys *ws = cmd_buffer->device->ws;
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const size_t src_stride = MAX2(stride, sizeof(VkDrawMeshTasksIndirectCommandNV));
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const size_t dst_stride = sizeof(VkDispatchIndirectCommand);
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const size_t src_off_task_count = offsetof(VkDrawMeshTasksIndirectCommandNV, taskCount);
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const size_t dst_off_x = offsetof(VkDispatchIndirectCommand, x);
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const unsigned new_disp_size = dst_stride * draw_count;
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const uint64_t va = radv_buffer_get_va(buffer->bo) + buffer->offset + offset;
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radv_cs_add_buffer(ws, cs, buffer->bo);
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/* Fill the buffer with X=0, Y=1, Z=1. */
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VkDispatchIndirectCommand *fill_data = (VkDispatchIndirectCommand *)alloca(new_disp_size);
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for (unsigned i = 0; i < draw_count; ++i) {
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fill_data[i].x = 0;
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fill_data[i].y = 1;
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fill_data[i].z = 1;
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}
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/* Allocate space in the upload BO. */
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unsigned out_offset;
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ASSERTED bool uploaded =
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radv_cmd_buffer_upload_data(cmd_buffer, new_disp_size, fill_data, &out_offset);
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const uint64_t new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + out_offset;
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assert(uploaded);
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/* Clamp draw count to fit the actual size of the buffer.
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* This is to avoid potential out of bounds copies (eg. for draws with an indirect count buffer).
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* The remaining indirect draws will stay filled with X=0, Y=1, Z=1 which is harmless.
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*/
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draw_count = MIN2(draw_count, (buffer->vk.size - buffer->offset - offset) / src_stride);
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ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 6 * draw_count + 2);
|
||||
|
||||
/* Copy taskCount from the NV API BO to the X dispatch size of the compatible BO. */
|
||||
for (unsigned i = 0; i < draw_count; ++i) {
|
||||
const uint64_t src_task_count = va + i * src_stride + src_off_task_count;
|
||||
const uint64_t dst_x = new_va + i * dst_stride + dst_off_x;
|
||||
|
||||
radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
|
||||
radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) | COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
|
||||
COPY_DATA_WR_CONFIRM);
|
||||
radeon_emit(cs, src_task_count);
|
||||
radeon_emit(cs, src_task_count >> 32);
|
||||
radeon_emit(cs, dst_x);
|
||||
radeon_emit(cs, dst_x >> 32);
|
||||
}
|
||||
|
||||
assert(cs->cdw <= cdw_max);
|
||||
|
||||
/* The draw packet can now use this buffer: */
|
||||
struct radv_buffer buf = *buffer;
|
||||
buf.bo = cmd_buffer->upload.upload_bo;
|
||||
buf.offset = out_offset;
|
||||
|
||||
return buf;
|
||||
}
|
||||
|
||||
VKAPI_ATTR void VKAPI_CALL
|
||||
radv_CmdDraw(VkCommandBuffer commandBuffer, uint32_t vertexCount, uint32_t instanceCount,
|
||||
uint32_t firstVertex, uint32_t firstInstance)
|
||||
|
|
@ -7574,16 +7900,7 @@ VKAPI_ATTR void VKAPI_CALL
|
|||
radv_CmdDrawMeshTasksNV(VkCommandBuffer commandBuffer, uint32_t taskCount, uint32_t firstTask)
|
||||
{
|
||||
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
|
||||
|
||||
ASSERTED struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
|
||||
assert(!pipeline->base.shaders[MESA_SHADER_TASK]);
|
||||
|
||||
/* Direct draw with mesh shader only.
|
||||
*
|
||||
* Use a non-indexed direct draw packet: DRAW_INDEX_AUTO.
|
||||
* As far as the HW is concerned: 1 input vertex = 1 mesh shader workgroup.
|
||||
*/
|
||||
|
||||
struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
|
||||
struct radv_draw_info info;
|
||||
|
||||
info.count = taskCount;
|
||||
|
|
@ -7598,7 +7915,12 @@ radv_CmdDrawMeshTasksNV(VkCommandBuffer commandBuffer, uint32_t taskCount, uint3
|
|||
if (!radv_before_taskmesh_draw(cmd_buffer, &info, 1))
|
||||
return;
|
||||
|
||||
radv_emit_direct_mesh_draw_packet(cmd_buffer, taskCount, 1, 1, firstTask);
|
||||
if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TASK)) {
|
||||
radv_emit_direct_taskmesh_draw_packets(cmd_buffer, taskCount, 1, 1, firstTask);
|
||||
} else {
|
||||
radv_emit_direct_mesh_draw_packet(cmd_buffer, taskCount, 1, 1, firstTask);
|
||||
}
|
||||
|
||||
radv_after_draw(cmd_buffer);
|
||||
}
|
||||
|
||||
|
|
@ -7609,28 +7931,13 @@ radv_CmdDrawMeshTasksIndirectNV(VkCommandBuffer commandBuffer, VkBuffer _buffer,
|
|||
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
|
||||
RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
|
||||
|
||||
ASSERTED struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
|
||||
assert(!pipeline->base.shaders[MESA_SHADER_TASK]);
|
||||
|
||||
/* Indirect draw with mesh shader only.
|
||||
*
|
||||
* Use DRAW_INDIRECT / DRAW_INDIRECT_MULTI like normal indirect draws.
|
||||
* We must use these draw commands for NV_mesh_shader because these
|
||||
* have firstVertex while the new DISPATCH_MESH_INDIRECT_MULTI
|
||||
* command doesn't have that.
|
||||
*
|
||||
* The indirect BO layout from the NV_mesh_shader API is not directly
|
||||
* compatible with AMD HW. To make it work, we allocate some space
|
||||
* in the upload buffer and copy the data to it.
|
||||
*/
|
||||
struct radv_buffer buf = radv_nv_mesh_indirect_bo(cmd_buffer, buffer, offset,
|
||||
drawCount, stride);
|
||||
struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
|
||||
struct radv_draw_info info;
|
||||
|
||||
info.indirect = buffer;
|
||||
info.indirect_offset = offset;
|
||||
info.stride = stride;
|
||||
info.count = drawCount;
|
||||
info.indirect = &buf;
|
||||
info.indirect_offset = 0;
|
||||
info.stride = sizeof(VkDrawIndirectCommand);
|
||||
info.strmout_buffer = NULL;
|
||||
info.count_buffer = NULL;
|
||||
info.indexed = false;
|
||||
|
|
@ -7638,7 +7945,41 @@ radv_CmdDrawMeshTasksIndirectNV(VkCommandBuffer commandBuffer, VkBuffer _buffer,
|
|||
|
||||
if (!radv_before_taskmesh_draw(cmd_buffer, &info, drawCount))
|
||||
return;
|
||||
radv_emit_indirect_draw_packets(cmd_buffer, &info);
|
||||
|
||||
/* Indirect draw with mesh shader only:
|
||||
* Use DRAW_INDIRECT / DRAW_INDIRECT_MULTI like normal indirect draws.
|
||||
* Needed because DISPATCH_MESH_INDIRECT_MULTI doesn't support firstTask.
|
||||
*
|
||||
* Indirect draw with task + mesh shaders:
|
||||
* Use DISPATCH_TASKMESH_INDIRECT_MULTI_ACE + DISPATCH_TASKMESH_GFX.
|
||||
* These packets don't support firstTask so we implement that by
|
||||
* reading the NV command's indirect buffer in the shader.
|
||||
*
|
||||
* The indirect BO layout from the NV_mesh_shader API is incompatible
|
||||
* with AMD HW. To make it work, we allocate some space
|
||||
* in the upload buffer and copy the data to it.
|
||||
*/
|
||||
|
||||
if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TASK)) {
|
||||
uint64_t nv_ib_va = radv_buffer_get_va(buffer->bo) + buffer->offset + offset;
|
||||
uint32_t nv_ib_stride = MAX2(stride, sizeof(VkDrawMeshTasksIndirectCommandNV));
|
||||
struct radv_buffer buf =
|
||||
radv_nv_task_indirect_bo(cmd_buffer, buffer, offset, drawCount, stride);
|
||||
info.indirect = &buf;
|
||||
info.indirect_offset = 0;
|
||||
info.stride = sizeof(VkDispatchIndirectCommand);
|
||||
|
||||
radv_emit_indirect_taskmesh_draw_packets(cmd_buffer, &info, nv_ib_va, nv_ib_stride);
|
||||
} else {
|
||||
struct radv_buffer buf =
|
||||
radv_nv_mesh_indirect_bo(cmd_buffer, buffer, offset, drawCount, stride);
|
||||
info.indirect = &buf;
|
||||
info.indirect_offset = 0;
|
||||
info.stride = sizeof(VkDrawIndirectCommand);
|
||||
|
||||
radv_emit_indirect_draw_packets(cmd_buffer, &info);
|
||||
}
|
||||
|
||||
radv_after_draw(cmd_buffer);
|
||||
}
|
||||
|
||||
|
|
@ -7652,17 +7993,13 @@ radv_CmdDrawMeshTasksIndirectCountNV(VkCommandBuffer commandBuffer, VkBuffer _bu
|
|||
RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
|
||||
RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
|
||||
|
||||
ASSERTED struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
|
||||
assert(!pipeline->base.shaders[MESA_SHADER_TASK]);
|
||||
|
||||
struct radv_buffer buf = radv_nv_mesh_indirect_bo(cmd_buffer, buffer, offset,
|
||||
maxDrawCount, stride);
|
||||
struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
|
||||
struct radv_draw_info info;
|
||||
|
||||
info.indirect = buffer;
|
||||
info.indirect_offset = offset;
|
||||
info.stride = stride;
|
||||
info.count = maxDrawCount;
|
||||
info.indirect = &buf;
|
||||
info.indirect_offset = 0;
|
||||
info.stride = sizeof(VkDrawIndirectCommand);
|
||||
info.strmout_buffer = NULL;
|
||||
info.count_buffer = count_buffer;
|
||||
info.count_buffer_offset = countBufferOffset;
|
||||
|
|
@ -7671,7 +8008,27 @@ radv_CmdDrawMeshTasksIndirectCountNV(VkCommandBuffer commandBuffer, VkBuffer _bu
|
|||
|
||||
if (!radv_before_taskmesh_draw(cmd_buffer, &info, maxDrawCount))
|
||||
return;
|
||||
radv_emit_indirect_draw_packets(cmd_buffer, &info);
|
||||
|
||||
if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TASK)) {
|
||||
uint64_t nv_ib_va = radv_buffer_get_va(buffer->bo) + buffer->offset + offset;
|
||||
uint32_t nv_ib_stride = MAX2(stride, sizeof(VkDrawMeshTasksIndirectCommandNV));
|
||||
struct radv_buffer buf =
|
||||
radv_nv_task_indirect_bo(cmd_buffer, buffer, offset, maxDrawCount, stride);
|
||||
info.indirect = &buf;
|
||||
info.indirect_offset = 0;
|
||||
info.stride = sizeof(VkDispatchIndirectCommand);
|
||||
|
||||
radv_emit_indirect_taskmesh_draw_packets(cmd_buffer, &info, nv_ib_va, nv_ib_stride);
|
||||
} else {
|
||||
struct radv_buffer buf =
|
||||
radv_nv_mesh_indirect_bo(cmd_buffer, buffer, offset, maxDrawCount, stride);
|
||||
info.indirect = &buf;
|
||||
info.indirect_offset = 0;
|
||||
info.stride = sizeof(VkDrawIndirectCommand);
|
||||
|
||||
radv_emit_indirect_draw_packets(cmd_buffer, &info);
|
||||
}
|
||||
|
||||
radv_after_draw(cmd_buffer);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue