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i965/fs: Feel free to spill partial reads/writes 

Now that we properly handle write-masking, this should be safe.
This commit is contained in:
Jason Ekstrand 2016-01-25 15:00:38 -08:00
parent 9c0109a1f6
commit 2434ceabf4
1 changed files with 2 additions and 19 deletions
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21
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
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@ -808,30 +808,13 @@ fs_visitor::choose_spill_reg(struct ra_graph *g)
*/
foreach_block_and_inst(block, fs_inst, inst, cfg) {
for (unsigned int i = 0; i < inst->sources; i++) {
if (inst->src[i].file == VGRF) {
if (inst->src[i].file == VGRF)
spill_costs[inst->src[i].nr] += loop_scale;
/* Register spilling logic assumes full-width registers; smeared
* registers have a width of 1 so if we try to spill them we'll
* generate invalid assembly. This shouldn't be a problem because
* smeared registers are only used as short-term temporaries when
* loading pull constants, so spilling them is unlikely to reduce
* register pressure anyhow.
*/
if (!inst->src[i].is_contiguous()) {
no_spill[inst->src[i].nr] = true;
}
}
}
if (inst->dst.file == VGRF) {
if (inst->dst.file == VGRF)
spill_costs[inst->dst.nr] += inst->regs_written * loop_scale;
if (!inst->dst.is_contiguous()) {
no_spill[inst->dst.nr] = true;
}
}
switch (inst->opcode) {
case BRW_OPCODE_DO: