radeonsi: properly check if DCC is enabled and allocated
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
parent
5bc5dca0cb
commit
235d38584c
|
@ -1367,7 +1367,7 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (tex->surface.dcc_enabled) {
|
if (tex->dcc_buffer) {
|
||||||
uint32_t reset_value;
|
uint32_t reset_value;
|
||||||
bool clear_words_needed;
|
bool clear_words_needed;
|
||||||
|
|
||||||
|
|
|
@ -243,7 +243,7 @@ void cik_sdma_copy(struct pipe_context *ctx,
|
||||||
if (src->format != dst->format ||
|
if (src->format != dst->format ||
|
||||||
rdst->surface.nsamples > 1 || rsrc->surface.nsamples > 1 ||
|
rdst->surface.nsamples > 1 || rsrc->surface.nsamples > 1 ||
|
||||||
(rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level) ||
|
(rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level) ||
|
||||||
rdst->surface.dcc_enabled || rsrc->surface.dcc_enabled) {
|
rdst->dcc_buffer || rsrc->dcc_buffer) {
|
||||||
goto fallback;
|
goto fallback;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -326,7 +326,7 @@ void si_decompress_color_textures(struct si_context *sctx,
|
||||||
assert(view);
|
assert(view);
|
||||||
|
|
||||||
tex = (struct r600_texture *)view->texture;
|
tex = (struct r600_texture *)view->texture;
|
||||||
assert(tex->cmask.size || tex->fmask.size || tex->surface.dcc_enabled);
|
assert(tex->cmask.size || tex->fmask.size || tex->dcc_buffer);
|
||||||
|
|
||||||
si_blit_decompress_color(&sctx->b.b, tex,
|
si_blit_decompress_color(&sctx->b.b, tex,
|
||||||
view->u.tex.first_level, view->u.tex.last_level,
|
view->u.tex.first_level, view->u.tex.last_level,
|
||||||
|
@ -455,7 +455,7 @@ static void si_decompress_subresource(struct pipe_context *ctx,
|
||||||
si_blit_decompress_depth_in_place(sctx, rtex, true,
|
si_blit_decompress_depth_in_place(sctx, rtex, true,
|
||||||
level, level,
|
level, level,
|
||||||
first_layer, last_layer);
|
first_layer, last_layer);
|
||||||
} else if (rtex->fmask.size || rtex->cmask.size || rtex->surface.dcc_enabled) {
|
} else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_buffer) {
|
||||||
si_blit_decompress_color(ctx, rtex, level, level,
|
si_blit_decompress_color(ctx, rtex, level, level,
|
||||||
first_layer, last_layer);
|
first_layer, last_layer);
|
||||||
}
|
}
|
||||||
|
@ -676,7 +676,7 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
|
||||||
dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
|
dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
|
||||||
!(dst->surface.flags & RADEON_SURF_SCANOUT) &&
|
!(dst->surface.flags & RADEON_SURF_SCANOUT) &&
|
||||||
(!dst->cmask.size || !dst->dirty_level_mask) && /* dst cannot be fast-cleared */
|
(!dst->cmask.size || !dst->dirty_level_mask) && /* dst cannot be fast-cleared */
|
||||||
!dst->surface.dcc_enabled) {
|
!dst->dcc_buffer) {
|
||||||
si_blitter_begin(ctx, SI_COLOR_RESOLVE |
|
si_blitter_begin(ctx, SI_COLOR_RESOLVE |
|
||||||
(info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
|
(info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
|
||||||
util_blitter_custom_resolve_color(sctx->blitter,
|
util_blitter_custom_resolve_color(sctx->blitter,
|
||||||
|
|
|
@ -249,7 +249,7 @@ void si_dma_copy(struct pipe_context *ctx,
|
||||||
(rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level) ||
|
(rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level) ||
|
||||||
rdst->cmask.size || rdst->fmask.size ||
|
rdst->cmask.size || rdst->fmask.size ||
|
||||||
rsrc->cmask.size || rsrc->fmask.size ||
|
rsrc->cmask.size || rsrc->fmask.size ||
|
||||||
rdst->surface.dcc_enabled || rsrc->surface.dcc_enabled) {
|
rdst->dcc_buffer || rsrc->dcc_buffer) {
|
||||||
goto fallback;
|
goto fallback;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -1926,7 +1926,7 @@ static void si_initialize_color_surface(struct si_context *sctx,
|
||||||
surf->cb_color_info = color_info;
|
surf->cb_color_info = color_info;
|
||||||
surf->cb_color_attrib = color_attrib;
|
surf->cb_color_attrib = color_attrib;
|
||||||
|
|
||||||
if (sctx->b.chip_class >= VI && rtex->surface.dcc_enabled) {
|
if (sctx->b.chip_class >= VI && rtex->dcc_buffer) {
|
||||||
unsigned max_uncompressed_block_size = 2;
|
unsigned max_uncompressed_block_size = 2;
|
||||||
uint64_t dcc_offset = rtex->surface.level[level].dcc_offset;
|
uint64_t dcc_offset = rtex->surface.level[level].dcc_offset;
|
||||||
|
|
||||||
|
@ -2655,7 +2655,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
|
||||||
view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
|
view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
|
||||||
S_008F24_LAST_ARRAY(last_layer));
|
S_008F24_LAST_ARRAY(last_layer));
|
||||||
|
|
||||||
if (tmp->surface.dcc_enabled) {
|
if (tmp->dcc_buffer) {
|
||||||
uint64_t dcc_offset = surflevel[base_level].dcc_offset;
|
uint64_t dcc_offset = surflevel[base_level].dcc_offset;
|
||||||
unsigned swap = r600_translate_colorswap(pipe_format);
|
unsigned swap = r600_translate_colorswap(pipe_format);
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue