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i965/compute: Fix undefined code with right_mask for SIMD32 

Although we don't support SIMD32, krh pointed out that the left shift
by 32 is undefined by C/C++ for 32-bit integers.

Suggested-by: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jordan Justen 2015-06-16 14:27:15 -07:00
parent 770f141866
commit 2310a65c28
1 changed files with 1 additions and 1 deletions
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src/mesa/drivers/dri/i965/brw_compute.c
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@ -45,7 +45,7 @@ brw_emit_gpgpu_walker(struct brw_context *brw, const GLuint *num_groups)
unsigned thread_width_max =
(group_size + simd_size - 1) / simd_size;
uint32_t right_mask = (1u << simd_size) - 1;
uint32_t right_mask = 0xffffffffu >> (32 - simd_size);
const unsigned right_non_aligned = group_size & (simd_size - 1);
if (right_non_aligned != 0)
right_mask >>= (simd_size - right_non_aligned);