gallium: separate indirect stuff from pipe_draw_info - 80 -> 56 bytes
For faster initialization of non-indirect draws.
This commit is contained in:
parent
c24c3b94ed
commit
22f6624ed3
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@ -145,8 +145,8 @@ util_draw_indirect(struct pipe_context *pipe,
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params = (uint32_t *)
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pipe_buffer_map_range(pipe,
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info_in->indirect,
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info_in->indirect_offset,
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info_in->indirect->buffer,
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info_in->indirect->offset,
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num_params * sizeof(uint32_t),
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PIPE_TRANSFER_READ,
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&transfer);
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@ -941,11 +941,16 @@ util_dump_draw_info(FILE *stream, const struct pipe_draw_info *state)
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util_dump_member(stream, ptr, state, count_from_stream_output);
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if (!state->indirect) {
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util_dump_member(stream, ptr, state, indirect);
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util_dump_member(stream, uint, state, indirect_offset);
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util_dump_member(stream, uint, state, indirect_stride);
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util_dump_member(stream, uint, state, indirect_count);
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util_dump_member(stream, uint, state, indirect_params_offset);
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} else {
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util_dump_member(stream, uint, state, indirect->offset);
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util_dump_member(stream, uint, state, indirect->stride);
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util_dump_member(stream, uint, state, indirect->draw_count);
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util_dump_member(stream, uint, state, indirect->indirect_draw_count_offset);
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util_dump_member(stream, ptr, state, indirect->buffer);
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util_dump_member(stream, ptr, state, indirect->indirect_draw_count);
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}
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util_dump_struct_end(stream);
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}
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@ -1168,15 +1168,15 @@ void u_vbuf_draw_vbo(struct u_vbuf *mgr, const struct pipe_draw_info *info)
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int *data;
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if (new_info.indexed) {
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data = pipe_buffer_map_range(pipe, new_info.indirect,
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new_info.indirect_offset, 20,
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data = pipe_buffer_map_range(pipe, new_info.indirect->buffer,
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new_info.indirect->offset, 20,
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PIPE_TRANSFER_READ, &transfer);
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new_info.index_bias = data[3];
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new_info.start_instance = data[4];
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}
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else {
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data = pipe_buffer_map_range(pipe, new_info.indirect,
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new_info.indirect_offset, 16,
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data = pipe_buffer_map_range(pipe, new_info.indirect->buffer,
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new_info.indirect->offset, 16,
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PIPE_TRANSFER_READ, &transfer);
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new_info.start_instance = data[3];
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}
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@ -217,7 +217,7 @@ The integer capabilities:
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pipe_draw_info::indirect_stride and ::indirect_count
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* ``PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS``: Whether the driver supports
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taking the number of indirect draws from a separate parameter
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buffer, see pipe_draw_info::indirect_params.
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buffer, see pipe_draw_indirect_info::indirect_draw_count.
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* ``PIPE_CAP_TGSI_FS_FINE_DERIVATIVE``: Whether the fragment shader supports
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the FINE versions of DDX/DDY.
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* ``PIPE_CAP_VENDOR_ID``: The vendor ID of the underlying hardware. If it's
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@ -297,10 +297,12 @@ dd_dump_draw_vbo(struct dd_draw_state *dstate, struct pipe_draw_info *info, FILE
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if (info->count_from_stream_output)
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DUMP_M(stream_output_target, info,
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count_from_stream_output);
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if (info->indirect)
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DUMP_M(resource, info, indirect);
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if (info->indirect_params)
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DUMP_M(resource, info, indirect_params);
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if (info->indirect) {
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DUMP_M(resource, info, indirect->buffer);
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if (info->indirect->indirect_draw_count)
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DUMP_M(resource, info, indirect->indirect_draw_count);
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}
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fprintf(f, "\n");
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/* TODO: dump active queries */
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@ -500,7 +502,7 @@ dd_dump_call(FILE *f, struct dd_draw_state *state, struct dd_call *call)
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{
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switch (call->type) {
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case CALL_DRAW_VBO:
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dd_dump_draw_vbo(state, &call->info.draw_vbo, f);
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dd_dump_draw_vbo(state, &call->info.draw_vbo.draw, f);
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break;
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case CALL_LAUNCH_GRID:
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dd_dump_launch_grid(state, &call->info.launch_grid, f);
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@ -619,9 +621,9 @@ dd_unreference_copy_of_call(struct dd_call *dst)
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{
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switch (dst->type) {
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case CALL_DRAW_VBO:
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pipe_so_target_reference(&dst->info.draw_vbo.count_from_stream_output, NULL);
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pipe_resource_reference(&dst->info.draw_vbo.indirect, NULL);
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pipe_resource_reference(&dst->info.draw_vbo.indirect_params, NULL);
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pipe_so_target_reference(&dst->info.draw_vbo.draw.count_from_stream_output, NULL);
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pipe_resource_reference(&dst->info.draw_vbo.indirect.buffer, NULL);
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pipe_resource_reference(&dst->info.draw_vbo.indirect.indirect_draw_count, NULL);
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break;
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case CALL_LAUNCH_GRID:
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pipe_resource_reference(&dst->info.launch_grid.indirect, NULL);
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@ -661,13 +663,17 @@ dd_copy_call(struct dd_call *dst, struct dd_call *src)
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switch (src->type) {
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case CALL_DRAW_VBO:
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pipe_so_target_reference(&dst->info.draw_vbo.count_from_stream_output,
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src->info.draw_vbo.count_from_stream_output);
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pipe_resource_reference(&dst->info.draw_vbo.indirect,
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src->info.draw_vbo.indirect);
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pipe_resource_reference(&dst->info.draw_vbo.indirect_params,
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src->info.draw_vbo.indirect_params);
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pipe_so_target_reference(&dst->info.draw_vbo.draw.count_from_stream_output,
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src->info.draw_vbo.draw.count_from_stream_output);
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pipe_resource_reference(&dst->info.draw_vbo.indirect.buffer,
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src->info.draw_vbo.indirect.buffer);
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pipe_resource_reference(&dst->info.draw_vbo.indirect.indirect_draw_count,
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src->info.draw_vbo.indirect.indirect_draw_count);
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dst->info.draw_vbo = src->info.draw_vbo;
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if (!src->info.draw_vbo.draw.indirect)
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dst->info.draw_vbo.draw.indirect = NULL;
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else
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dst->info.draw_vbo.draw.indirect = &dst->info.draw_vbo.indirect;
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break;
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case CALL_LAUNCH_GRID:
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pipe_resource_reference(&dst->info.launch_grid.indirect,
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@ -1173,7 +1179,13 @@ dd_context_draw_vbo(struct pipe_context *_pipe,
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struct dd_call call;
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call.type = CALL_DRAW_VBO;
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call.info.draw_vbo = *info;
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call.info.draw_vbo.draw = *info;
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if (info->indirect) {
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call.info.draw_vbo.indirect = *info->indirect;
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call.info.draw_vbo.draw.indirect = &call.info.draw_vbo.indirect;
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} else {
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memset(&call.info.draw_vbo.indirect, 0, sizeof(*info->indirect));
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}
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dd_before_draw(dctx);
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pipe->draw_vbo(pipe, info);
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@ -104,12 +104,17 @@ struct call_generate_mipmap {
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unsigned last_layer;
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};
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struct call_draw_info {
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struct pipe_draw_info draw;
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struct pipe_draw_indirect_info indirect;
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};
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struct dd_call
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{
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enum call_type type;
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union {
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struct pipe_draw_info draw_vbo;
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struct call_draw_info draw_vbo;
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struct pipe_grid_info launch_grid;
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struct call_resource_copy_region resource_copy_region;
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struct pipe_blit_info blit;
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@ -818,10 +818,10 @@ static void
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nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info)
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{
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struct nouveau_pushbuf *push = nvc0->base.pushbuf;
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struct nv04_resource *buf = nv04_resource(info->indirect);
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struct nv04_resource *buf_count = nv04_resource(info->indirect_params);
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unsigned size, macro, count = info->indirect_count, drawid = info->drawid;
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uint32_t offset = buf->offset + info->indirect_offset;
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struct nv04_resource *buf = nv04_resource(info->indirect->buffer);
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struct nv04_resource *buf_count = nv04_resource(info->indirect->indirect_draw_count);
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unsigned size, macro, count = info->indirect->draw_count, drawid = info->drawid;
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uint32_t offset = buf->offset + info->indirect->offset;
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struct nvc0_screen *screen = nvc0->screen;
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PUSH_SPACE(push, 7);
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@ -870,7 +870,7 @@ nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info)
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*/
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while (count) {
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unsigned draws = count, pushes, i;
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if (info->indirect_stride == size * 4) {
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if (info->indirect->stride == size * 4) {
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draws = MIN2(draws, (NV04_PFIFO_MAX_PACKET_LEN - 4) / size);
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pushes = 1;
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} else {
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@ -890,20 +890,20 @@ nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info)
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if (buf_count) {
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nouveau_pushbuf_data(push,
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buf_count->bo,
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buf_count->offset + info->indirect_params_offset,
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buf_count->offset + info->indirect->indirect_draw_count_offset,
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NVC0_IB_ENTRY_1_NO_PREFETCH | 4);
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}
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if (pushes == 1) {
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nouveau_pushbuf_data(push,
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buf->bo, offset,
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NVC0_IB_ENTRY_1_NO_PREFETCH | (size * 4 * draws));
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offset += draws * info->indirect_stride;
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offset += draws * info->indirect->stride;
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} else {
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for (i = 0; i < pushes; i++) {
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nouveau_pushbuf_data(push,
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buf->bo, offset,
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NVC0_IB_ENTRY_1_NO_PREFETCH | (size * 4));
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offset += info->indirect_stride;
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offset += info->indirect->stride;
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}
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}
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count -= draws;
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@ -1770,11 +1770,11 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
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}
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else {
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/* Have to get start/count from indirect buffer, slow path ahead... */
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struct r600_resource *indirect_resource = (struct r600_resource *)info->indirect;
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struct r600_resource *indirect_resource = (struct r600_resource *)info->indirect->buffer;
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unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource,
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PIPE_TRANSFER_READ);
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if (data) {
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data += info->indirect_offset / sizeof(unsigned);
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data += info->indirect->offset / sizeof(unsigned);
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start = data[2] * ib.index_size;
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count = data[0];
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}
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@ -1918,7 +1918,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
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radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
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radeon_emit(cs, info->instance_count);
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} else {
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uint64_t va = r600_resource(info->indirect)->gpu_address;
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uint64_t va = r600_resource(info->indirect->buffer)->gpu_address;
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assert(rctx->b.chip_class >= EVERGREEN);
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// Invalidate so non-indirect draw calls reset this state
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@ -1932,7 +1932,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
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radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
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(struct r600_resource*)info->indirect,
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(struct r600_resource*)info->indirect->buffer,
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RADEON_USAGE_READ,
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RADEON_PRIO_DRAW_INDIRECT));
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}
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@ -1982,7 +1982,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
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radeon_emit(cs, max_size);
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radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, render_cond_bit));
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radeon_emit(cs, info->indirect_offset);
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radeon_emit(cs, info->indirect->offset);
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radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
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}
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}
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@ -2012,7 +2012,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
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}
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else {
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radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDIRECT, 1, render_cond_bit));
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radeon_emit(cs, info->indirect_offset);
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radeon_emit(cs, info->indirect->offset);
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}
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radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
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(info->count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0));
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@ -627,6 +627,7 @@ static void si_emit_draw_packets(struct si_context *sctx,
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const struct pipe_draw_info *info,
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const struct pipe_index_buffer *ib)
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{
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struct pipe_draw_indirect_info *indirect = info->indirect;
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struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
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unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
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bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
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@ -707,8 +708,8 @@ static void si_emit_draw_packets(struct si_context *sctx,
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sctx->last_index_size = -1;
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}
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if (info->indirect) {
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uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
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if (indirect) {
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uint64_t indirect_va = r600_resource(indirect->buffer)->gpu_address;
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assert(indirect_va % 8 == 0);
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@ -720,13 +721,13 @@ static void si_emit_draw_packets(struct si_context *sctx,
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radeon_emit(cs, indirect_va >> 32);
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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(struct r600_resource *)info->indirect,
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(struct r600_resource *)indirect->buffer,
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RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
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unsigned di_src_sel = info->indexed ? V_0287F0_DI_SRC_SEL_DMA
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: V_0287F0_DI_SRC_SEL_AUTO_INDEX;
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assert(info->indirect_offset % 4 == 0);
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assert(indirect->offset % 4 == 0);
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if (info->indexed) {
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radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
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@ -741,37 +742,37 @@ static void si_emit_draw_packets(struct si_context *sctx,
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radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT
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: PKT3_DRAW_INDIRECT,
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3, render_cond_bit));
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radeon_emit(cs, info->indirect_offset);
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radeon_emit(cs, indirect->offset);
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radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
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radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
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radeon_emit(cs, di_src_sel);
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} else {
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uint64_t count_va = 0;
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if (info->indirect_params) {
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if (indirect->indirect_draw_count) {
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struct r600_resource *params_buf =
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(struct r600_resource *)info->indirect_params;
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(struct r600_resource *)indirect->indirect_draw_count;
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radeon_add_to_buffer_list(
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&sctx->b, &sctx->b.gfx, params_buf,
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RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
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count_va = params_buf->gpu_address + info->indirect_params_offset;
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count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
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}
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radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
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PKT3_DRAW_INDIRECT_MULTI,
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8, render_cond_bit));
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radeon_emit(cs, info->indirect_offset);
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radeon_emit(cs, indirect->offset);
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radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
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radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
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radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
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S_2C3_DRAW_INDEX_ENABLE(1) |
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S_2C3_COUNT_INDIRECT_ENABLE(!!info->indirect_params));
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radeon_emit(cs, info->indirect_count);
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S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
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radeon_emit(cs, indirect->draw_count);
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radeon_emit(cs, count_va);
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radeon_emit(cs, count_va >> 32);
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radeon_emit(cs, info->indirect_stride);
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radeon_emit(cs, indirect->stride);
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radeon_emit(cs, di_src_sel);
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}
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} else {
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@ -1072,17 +1073,19 @@ static void si_get_draw_start_count(struct si_context *sctx,
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const struct pipe_draw_info *info,
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unsigned *start, unsigned *count)
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{
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if (info->indirect) {
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struct pipe_draw_indirect_info *indirect = info->indirect;
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if (indirect) {
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unsigned indirect_count;
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struct pipe_transfer *transfer;
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unsigned begin, end;
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unsigned map_size;
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unsigned *data;
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if (info->indirect_params) {
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if (indirect->indirect_draw_count) {
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data = pipe_buffer_map_range(&sctx->b.b,
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info->indirect_params,
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info->indirect_params_offset,
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indirect->indirect_draw_count,
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indirect->indirect_draw_count_offset,
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sizeof(unsigned),
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PIPE_TRANSFER_READ, &transfer);
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@ -1090,7 +1093,7 @@ static void si_get_draw_start_count(struct si_context *sctx,
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|||
|
||||
pipe_buffer_unmap(&sctx->b.b, transfer);
|
||||
} else {
|
||||
indirect_count = info->indirect_count;
|
||||
indirect_count = indirect->draw_count;
|
||||
}
|
||||
|
||||
if (!indirect_count) {
|
||||
|
@ -1098,9 +1101,9 @@ static void si_get_draw_start_count(struct si_context *sctx,
|
|||
return;
|
||||
}
|
||||
|
||||
map_size = (indirect_count - 1) * info->indirect_stride + 3 * sizeof(unsigned);
|
||||
data = pipe_buffer_map_range(&sctx->b.b, info->indirect,
|
||||
info->indirect_offset, map_size,
|
||||
map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
|
||||
data = pipe_buffer_map_range(&sctx->b.b, indirect->buffer,
|
||||
indirect->offset, map_size,
|
||||
PIPE_TRANSFER_READ, &transfer);
|
||||
|
||||
begin = UINT_MAX;
|
||||
|
@ -1115,7 +1118,7 @@ static void si_get_draw_start_count(struct si_context *sctx,
|
|||
end = MAX2(end, start + count);
|
||||
}
|
||||
|
||||
data += info->indirect_stride / sizeof(unsigned);
|
||||
data += indirect->stride / sizeof(unsigned);
|
||||
}
|
||||
|
||||
pipe_buffer_unmap(&sctx->b.b, transfer);
|
||||
|
@ -1301,18 +1304,20 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
|
|||
}
|
||||
|
||||
if (info->indirect) {
|
||||
/* Add the buffer size for memory checking in need_cs_space. */
|
||||
r600_context_add_resource_size(ctx, info->indirect);
|
||||
struct pipe_draw_indirect_info *indirect = info->indirect;
|
||||
|
||||
if (r600_resource(info->indirect)->TC_L2_dirty) {
|
||||
/* Add the buffer size for memory checking in need_cs_space. */
|
||||
r600_context_add_resource_size(ctx, indirect->buffer);
|
||||
|
||||
if (r600_resource(indirect->buffer)->TC_L2_dirty) {
|
||||
sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
|
||||
r600_resource(info->indirect)->TC_L2_dirty = false;
|
||||
r600_resource(indirect->buffer)->TC_L2_dirty = false;
|
||||
}
|
||||
|
||||
if (info->indirect_params &&
|
||||
r600_resource(info->indirect_params)->TC_L2_dirty) {
|
||||
if (indirect->indirect_draw_count &&
|
||||
r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
|
||||
sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
|
||||
r600_resource(info->indirect_params)->TC_L2_dirty = false;
|
||||
r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -812,8 +812,16 @@ void trace_dump_draw_info(const struct pipe_draw_info *state)
|
|||
|
||||
trace_dump_member(ptr, state, count_from_stream_output);
|
||||
|
||||
if (!state->indirect) {
|
||||
trace_dump_member(ptr, state, indirect);
|
||||
trace_dump_member(uint, state, indirect_offset);
|
||||
} else {
|
||||
trace_dump_member(uint, state, indirect->offset);
|
||||
trace_dump_member(uint, state, indirect->stride);
|
||||
trace_dump_member(uint, state, indirect->draw_count);
|
||||
trace_dump_member(uint, state, indirect->indirect_draw_count_offset);
|
||||
trace_dump_member(ptr, state, indirect->buffer);
|
||||
trace_dump_member(ptr, state, indirect->indirect_draw_count);
|
||||
}
|
||||
|
||||
trace_dump_struct_end();
|
||||
}
|
||||
|
|
|
@ -641,6 +641,40 @@ struct pipe_index_buffer
|
|||
};
|
||||
|
||||
|
||||
struct pipe_draw_indirect_info
|
||||
{
|
||||
unsigned offset; /**< must be 4 byte aligned */
|
||||
unsigned stride; /**< must be 4 byte aligned */
|
||||
unsigned draw_count; /**< number of indirect draws */
|
||||
unsigned indirect_draw_count_offset; /**< must be 4 byte aligned */
|
||||
|
||||
/* Indirect draw parameters resource is laid out as follows:
|
||||
*
|
||||
* if indexed is TRUE:
|
||||
* struct {
|
||||
* uint32_t count;
|
||||
* uint32_t instance_count;
|
||||
* uint32_t start;
|
||||
* int32_t index_bias;
|
||||
* uint32_t start_instance;
|
||||
* };
|
||||
* otherwise:
|
||||
* struct {
|
||||
* uint32_t count;
|
||||
* uint32_t instance_count;
|
||||
* uint32_t start;
|
||||
* uint32_t start_instance;
|
||||
* };
|
||||
*/
|
||||
struct pipe_resource *buffer;
|
||||
|
||||
/* Indirect draw count resource: If not NULL, contains a 32-bit value which
|
||||
* is to be used as the real draw_count.
|
||||
*/
|
||||
struct pipe_resource *indirect_draw_count;
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* Information to describe a draw_vbo call.
|
||||
*/
|
||||
|
@ -671,40 +705,9 @@ struct pipe_draw_info
|
|||
*/
|
||||
unsigned restart_index;
|
||||
|
||||
unsigned indirect_offset; /**< must be 4 byte aligned */
|
||||
unsigned indirect_stride; /**< must be 4 byte aligned */
|
||||
unsigned indirect_count; /**< number of indirect draws */
|
||||
|
||||
unsigned indirect_params_offset; /**< must be 4 byte aligned */
|
||||
|
||||
/* Pointers must be at the end for an optimal structure layout on 64-bit. */
|
||||
|
||||
/* Indirect draw parameters resource: If not NULL, most values are taken
|
||||
* from this buffer instead, which is laid out as follows:
|
||||
*
|
||||
* if indexed is TRUE:
|
||||
* struct {
|
||||
* uint32_t count;
|
||||
* uint32_t instance_count;
|
||||
* uint32_t start;
|
||||
* int32_t index_bias;
|
||||
* uint32_t start_instance;
|
||||
* };
|
||||
* otherwise:
|
||||
* struct {
|
||||
* uint32_t count;
|
||||
* uint32_t instance_count;
|
||||
* uint32_t start;
|
||||
* uint32_t start_instance;
|
||||
* };
|
||||
*/
|
||||
struct pipe_resource *indirect;
|
||||
|
||||
/* Indirect draw count resource: If not NULL, contains a 32-bit value which
|
||||
* is to be used as the real indirect_count. In that case indirect_count
|
||||
* becomes the maximum possible value.
|
||||
*/
|
||||
struct pipe_resource *indirect_params;
|
||||
struct pipe_draw_indirect_info *indirect; /**< Indirect draw. */
|
||||
|
||||
/**
|
||||
* Stream output target. If not NULL, it's used to provide the 'count'
|
||||
|
|
|
@ -3031,7 +3031,6 @@ NineDevice9_ProcessVertices( struct NineDevice9 *This,
|
|||
draw.restart_index = 0;
|
||||
draw.count_from_stream_output = NULL;
|
||||
draw.indirect = NULL;
|
||||
draw.indirect_params = NULL;
|
||||
draw.instance_count = 1;
|
||||
draw.indexed = FALSE;
|
||||
draw.start = 0;
|
||||
|
|
|
@ -2559,7 +2559,6 @@ init_draw_info(struct pipe_draw_info *info,
|
|||
info->restart_index = 0;
|
||||
info->count_from_stream_output = NULL;
|
||||
info->indirect = NULL;
|
||||
info->indirect_params = NULL;
|
||||
}
|
||||
|
||||
CSMT_ITEM_NO_WAIT(nine_context_draw_primitive,
|
||||
|
|
|
@ -264,6 +264,7 @@ st_indirect_draw_vbo(struct gl_context *ctx,
|
|||
{
|
||||
struct st_context *st = st_context(ctx);
|
||||
struct pipe_draw_info info;
|
||||
struct pipe_draw_indirect_info indirect;
|
||||
|
||||
/* Mesa core state should have been validated already */
|
||||
assert(ctx->NewState == 0x0);
|
||||
|
@ -281,6 +282,7 @@ st_indirect_draw_vbo(struct gl_context *ctx,
|
|||
return;
|
||||
}
|
||||
|
||||
memset(&indirect, 0, sizeof(indirect));
|
||||
util_draw_init_info(&info);
|
||||
|
||||
if (ib) {
|
||||
|
@ -294,8 +296,9 @@ st_indirect_draw_vbo(struct gl_context *ctx,
|
|||
|
||||
info.mode = translate_prim(ctx, mode);
|
||||
info.vertices_per_patch = ctx->TessCtrlProgram.patch_vertices;
|
||||
info.indirect = st_buffer_object(indirect_data)->buffer;
|
||||
info.indirect_offset = indirect_offset;
|
||||
info.indirect = &indirect;
|
||||
indirect.buffer = st_buffer_object(indirect_data)->buffer;
|
||||
indirect.offset = indirect_offset;
|
||||
|
||||
if (ST_DEBUG & DEBUG_DRAW) {
|
||||
debug_printf("st/draw indirect: mode %s drawcount %d indexed %d\n",
|
||||
|
@ -308,18 +311,18 @@ st_indirect_draw_vbo(struct gl_context *ctx,
|
|||
int i;
|
||||
|
||||
assert(!indirect_params);
|
||||
info.indirect_count = 1;
|
||||
indirect.draw_count = 1;
|
||||
for (i = 0; i < draw_count; i++) {
|
||||
info.drawid = i;
|
||||
cso_draw_vbo(st->cso_context, &info);
|
||||
info.indirect_offset += stride;
|
||||
indirect.offset += stride;
|
||||
}
|
||||
} else {
|
||||
info.indirect_count = draw_count;
|
||||
info.indirect_stride = stride;
|
||||
indirect.draw_count = draw_count;
|
||||
indirect.stride = stride;
|
||||
if (indirect_params) {
|
||||
info.indirect_params = st_buffer_object(indirect_params)->buffer;
|
||||
info.indirect_params_offset = indirect_params_offset;
|
||||
indirect.indirect_draw_count = st_buffer_object(indirect_params)->buffer;
|
||||
indirect.indirect_draw_count_offset = indirect_params_offset;
|
||||
}
|
||||
cso_draw_vbo(st->cso_context, &info);
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue