i965/hsw: Change L3 MOCS of 3DSTATE_CONSTANT_VS/PS
Change from "not cacheable" to "cacheable" in L3. Do so for the draw upload path and blorp. In blorp, change only the PS packet, because the VS packet is disabled. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
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@ -616,6 +616,8 @@ gen7_blorp_emit_constant_ps(struct brw_context *brw,
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const brw_blorp_params *params,
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uint32_t wm_push_const_offset)
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{
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uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
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/* Make sure the push constants fill an exact integer number of
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* registers.
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*/
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@ -630,7 +632,7 @@ gen7_blorp_emit_constant_ps(struct brw_context *brw,
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(7 - 2));
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OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
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OUT_BATCH(0);
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OUT_BATCH(wm_push_const_offset);
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OUT_BATCH(wm_push_const_offset | mocs);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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@ -63,6 +63,8 @@ upload_vs_state(struct brw_context *brw)
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OUT_BATCH(0);
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ADVANCE_BATCH();
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} else {
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uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
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BEGIN_BATCH(7);
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OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
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OUT_BATCH(brw->vs.push_const_size);
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@ -70,7 +72,7 @@ upload_vs_state(struct brw_context *brw)
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/* Pointer to the VS constant buffer. Covered by the set of
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* state flags from gen6_prepare_wm_contants
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*/
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OUT_BATCH(brw->vs.push_const_offset);
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OUT_BATCH(brw->vs.push_const_offset | mocs);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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@ -141,6 +141,8 @@ upload_ps_state(struct brw_context *brw)
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OUT_BATCH(0);
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ADVANCE_BATCH();
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} else {
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uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
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BEGIN_BATCH(7);
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OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
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@ -150,7 +152,7 @@ upload_ps_state(struct brw_context *brw)
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/* Pointer to the WM constant buffer. Covered by the set of
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* state flags from gen6_upload_wm_push_constants.
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*/
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OUT_BATCH(brw->wm.push_const_offset);
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OUT_BATCH(brw->wm.push_const_offset | mocs);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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