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glsl: Remove ir_unop_any. 

The GLSL IR to TGSI/Mesa IR paths for any_nequal have the same
optimizations the ir_unop_any paths had.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
This commit is contained in:
Matt Turner 2015-11-30 11:56:31 -08:00
parent 249bb89617
commit 2268a50ffd
9 changed files with 5 additions and 165 deletions
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5
src/glsl/ir.cpp
View File

@ -307,10 +307,6 @@ ir_expression::ir_expression(int op, ir_rvalue *op0)
this->type = glsl_type::uvec2_type;
break;
case ir_unop_any:
this->type = glsl_type::bool_type;
break;
case ir_unop_pack_snorm_2x16:
case ir_unop_pack_snorm_4x8:
case ir_unop_pack_unorm_2x16:
@ -538,7 +534,6 @@ static const char *const operator_strs[] = {
"bitcast_f2i",
"bitcast_u2f",
"bitcast_f2u",
"any",
"trunc",
"ceil",
"floor",

2
src/glsl/ir.h
View File

@ -1355,7 +1355,6 @@ enum ir_expression_operation {
ir_unop_bitcast_f2i, /**< Bit-identical float-to-int "conversion" */
ir_unop_bitcast_u2f, /**< Bit-identical uint-to-float "conversion" */
ir_unop_bitcast_f2u, /**< Bit-identical float-to-uint "conversion" */
ir_unop_any,
/**
* \name Unary floating-point rounding operations.
@ -1726,7 +1725,6 @@ public:
{
return operation == ir_binop_all_equal ||
operation == ir_binop_any_nequal ||
operation == ir_unop_any ||
operation == ir_binop_dot ||
operation == ir_quadop_vector;
}

8
src/glsl/ir_constant_expression.cpp
View File

@ -648,14 +648,6 @@ ir_expression::constant_expression_value(struct hash_table *variable_context)
data.u[c] = bitcast_f2u(op[0]->value.f[c]);
}
break;
case ir_unop_any:
assert(op[0]->type->is_boolean());
data.b[0] = false;
for (unsigned c = 0; c < op[0]->type->components(); c++) {
if (op[0]->value.b[c])
data.b[0] = true;
}
break;
case ir_unop_d2f:
assert(op[0]->type->base_type == GLSL_TYPE_DOUBLE);
for (unsigned c = 0; c < op[0]->type->components(); c++) {

5
src/glsl/ir_validate.cpp
View File

@ -320,11 +320,6 @@ ir_validate::visit_leave(ir_expression *ir)
assert(ir->type->base_type == GLSL_TYPE_UINT);
break;
case ir_unop_any:
assert(ir->operands[0]->type->base_type == GLSL_TYPE_BOOL);
assert(ir->type == glsl_type::bool_type);
break;
case ir_unop_trunc:
case ir_unop_round_even:
case ir_unop_ceil:

6
src/glsl/lower_mat_op_to_vec.cpp
View File

@ -277,7 +277,11 @@ ir_mat_op_to_vec_visitor::do_equal_mat_mat(ir_dereference *result,
}
ir_rvalue *const val = new(this->mem_ctx) ir_dereference_variable(tmp_bvec);
ir_expression *any = new(this->mem_ctx) ir_expression(ir_unop_any, val);
uint8_t vec_elems = val->type->vector_elements;
ir_expression *any =
new(this->mem_ctx) ir_expression(ir_binop_any_nequal, val,
new(this->mem_ctx) ir_constant(false,
vec_elems));
if (test_equal)
any = new(this->mem_ctx) ir_expression(ir_unop_logic_not, any);

18
src/glsl/nir/glsl_to_nir.cpp
View File

@ -1417,24 +1417,6 @@ nir_visitor::visit(ir_expression *ir)
/* no-op */
result = nir_imov(&b, srcs[0]);
break;
case ir_unop_any:
switch (ir->operands[0]->type->vector_elements) {
case 2:
result = supports_ints ? nir_bany2(&b, srcs[0])
: nir_fany2(&b, srcs[0]);
break;
case 3:
result = supports_ints ? nir_bany3(&b, srcs[0])
: nir_fany3(&b, srcs[0]);
break;
case 4:
result = supports_ints ? nir_bany4(&b, srcs[0])
: nir_fany4(&b, srcs[0]);
break;
default:
unreachable("not reached");
}
break;
case ir_unop_trunc: result = nir_ftrunc(&b, srcs[0]); break;
case ir_unop_ceil: result = nir_fceil(&b, srcs[0]); break;
case ir_unop_floor: result = nir_ffloor(&b, srcs[0]); break;

17
src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
View File

@ -288,23 +288,6 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment *ir)
}
break;
case ir_unop_any: {
ir_expression *temp;
temp = new(mem_ctx) ir_expression(ir_binop_logic_or,
element_type,
get_element(op_var[0], 0),
get_element(op_var[0], 1));
for (i = 2; i < vector_elements; i++) {
temp = new(mem_ctx) ir_expression(ir_binop_logic_or,
element_type,
get_element(op_var[0], i),
temp);
}
assign(ir, 0, temp);
break;
}
case ir_binop_dot: {
ir_expression *last = NULL;
for (i = 0; i < vector_elements; i++) {

26
src/mesa/program/ir_to_mesa.cpp
View File

@ -1145,32 +1145,6 @@ ir_to_mesa_visitor::visit(ir_expression *ir)
}
break;
case ir_unop_any: {
assert(ir->operands[0]->type->is_vector());
/* After the dot-product, the value will be an integer on the
* range [0,4]. Zero stays zero, and positive values become 1.0.
*/
ir_to_mesa_instruction *const dp =
emit_dp(ir, result_dst, op[0], op[0],
ir->operands[0]->type->vector_elements);
if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
/* The clamping to [0,1] can be done for free in the fragment
* shader with a saturate.
*/
dp->saturate = true;
} else {
/* Negating the result of the dot-product gives values on the range
* [-4, 0]. Zero stays zero, and negative values become 1.0. This
* is achieved using SLT.
*/
src_reg slt_src = result_src;
slt_src.negate = ~slt_src.negate;
emit(ir, OPCODE_SLT, result_dst, slt_src, src_reg_for_float(0.0));
}
break;
}
case ir_binop_logic_xor:
emit(ir, OPCODE_SNE, result_dst, op[0], op[1]);
break;

83
src/mesa/state_tracker/st_glsl_to_tgsi.cpp
View File

@ -1776,89 +1776,6 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir)
}
break;
case ir_unop_any: {
assert(ir->operands[0]->type->is_vector());
if (native_integers) {
int dst_swizzle = 0, op0_swizzle, i;
st_src_reg accum = op[0];
op0_swizzle = op[0].swizzle;
accum.swizzle = MAKE_SWIZZLE4(GET_SWZ(op0_swizzle, 0),
GET_SWZ(op0_swizzle, 0),
GET_SWZ(op0_swizzle, 0),
GET_SWZ(op0_swizzle, 0));
for (i = 0; i < 4; i++) {
if (result_dst.writemask & (1 << i)) {
dst_swizzle = MAKE_SWIZZLE4(i, i, i, i);
break;
}
}
assert(i != 4);
assert(ir->operands[0]->type->is_boolean());
/* OR all the components together, since they should be either 0 or ~0
*/
switch (ir->operands[0]->type->vector_elements) {
case 4:
op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(op0_swizzle, 3),
GET_SWZ(op0_swizzle, 3),
GET_SWZ(op0_swizzle, 3),
GET_SWZ(op0_swizzle, 3));
emit_asm(ir, TGSI_OPCODE_OR, result_dst, accum, op[0]);
accum = st_src_reg(result_dst);
accum.swizzle = dst_swizzle;
/* fallthrough */
case 3:
op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(op0_swizzle, 2),
GET_SWZ(op0_swizzle, 2),
GET_SWZ(op0_swizzle, 2),
GET_SWZ(op0_swizzle, 2));
emit_asm(ir, TGSI_OPCODE_OR, result_dst, accum, op[0]);
accum = st_src_reg(result_dst);
accum.swizzle = dst_swizzle;
/* fallthrough */
case 2:
op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(op0_swizzle, 1),
GET_SWZ(op0_swizzle, 1),
GET_SWZ(op0_swizzle, 1),
GET_SWZ(op0_swizzle, 1));
emit_asm(ir, TGSI_OPCODE_OR, result_dst, accum, op[0]);
break;
default:
assert(!"Unexpected vector size");
break;
}
} else {
/* After the dot-product, the value will be an integer on the
* range [0,4]. Zero stays zero, and positive values become 1.0.
*/
glsl_to_tgsi_instruction *const dp =
emit_dp(ir, result_dst, op[0], op[0],
ir->operands[0]->type->vector_elements);
if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB &&
result_dst.type == GLSL_TYPE_FLOAT) {
/* The clamping to [0,1] can be done for free in the fragment
* shader with a saturate.
*/
dp->saturate = true;
} else if (result_dst.type == GLSL_TYPE_FLOAT) {
/* Negating the result of the dot-product gives values on the range
* [-4, 0]. Zero stays zero, and negative values become 1.0. This
* is achieved using SLT.
*/
st_src_reg slt_src = result_src;
slt_src.negate = ~slt_src.negate;
emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src, st_src_reg_for_float(0.0));
}
else {
/* Use SNE 0 if integers are being used as boolean values. */
emit_asm(ir, TGSI_OPCODE_SNE, result_dst, result_src, st_src_reg_for_int(0));
}
}
break;
}
case ir_binop_logic_xor:
if (native_integers)
emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);